Abstract: A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.1, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.

Abstract: A wafer bonding method for forming a SOI structure comprising the steps of bringing wafers into proximity in a state with one wafer a slight, substantially uniform clearance away from the other wafer and pressing one point of at least one wafer of the two wafers against the other wafer. In another aspect of the invention, there is provided a method of positioning for photolithography using an alignment mark portions and/or a vernier portions formed on a SOI substrate, which comprises the step of removing semiconductor layer portions corresponding to the alignment mark portions and/or the vernier portions. In further another aspect of the invention, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a new pattern of a strage node formed longitudinally along a word line. Further, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a unique strage node having a conductive side wall.

Abstract: A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.

Abstract: A wafer bonding method for forming a SOI structure comprising the steps of bringing wafers into proximity in a state with one wafer a slight, substantially uniform clearance away from the other wafer and pressing one point of at least one wafer of the two wafers against the other wafer. In another aspect of the invention, there is provided a method of positioning for photolithography using an alignment mark portions and/or a vernier portions formed on a SOI substrate, which comprises the step of removing semiconductor layer portions corresponding to the alignment mark portions and/or the vernier portions. In further another aspect of the invention, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a new pattern of a strage node formed longitudinally along a word line. Further, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a unique strage node having a conductive side wall.

Abstract: A wafer bonding method for forming a SOI structure comprising the steps of bringing wafers into proximity in a state with one wafer a slight, substantially uniform clearance away from the other wafer and pressing one point of at least one wafer of the two wafers against the other wafer. In another aspect of the invention, there is provided a method of positioning for photolithography using an alignment mark portions and/or a vernier portions formed on a SOI substrate, which comprises the step of removing semiconductor layer portions corresponding to the alignment mark portions and/or the vernier portions. In further another aspect of the invention, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a new pattern of a strage node formed longitudinally along a word line. Further, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a unique strage node having a conductive side wall.

Abstract: Disclosed herein is a solar cell which is composed basically of a first semiconductor layer of first conductivity type, a second semiconductor layer of second conductivity type, and a third semiconductor layer formed between them. The third semiconductor layer has a band gap narrower than that of the first and second semiconductor layers. The third semiconductor layer also has a pn junction therein. The semiconductor layers are each separated by a buffer layer in which the composition changes gradually across the thickness so that the lattice mismatch between the semiconductor layers is relieved.

Abstract: The invention concerns a method of forming various kinds of SOI structures and semiconductor memory devices using the forming technique. It is useful, for example, in SRAM or EEPROM devices. In EEPROM, it relates, in particular, to a method of manufacturing a non-volatile memory device in which a control gate electrode layer is laminated by way of an insulator film on a floating gate electrode layer. It includes a method of manufacturing a structure via the steps of forming an etching stopping layer on the surface of a silicon substrate, forming an epitaxially grown silicon layer on said etching stopping layer, bonding said silicon substrate formed with said silicon layer with another substrate as the insulator substrate, grinding said silicon substrate from the rear face and etching it until said etching stopping layer is exposed and removing said etching stopper layer, with or without polishing the other surface of said silicon substrate.

Abstract: A wafer bonding method for forming a SOI structure comprising the steps of bringing wafers into proximity in a state with one wafer a slight, substantially uniform clearance away from the other wafer and pressing one point of at least one wafer of the two wafers against the other wafer. In another aspect of the invention, there is provided a method of positioning for photolithography using an alignment mark portions and/or a vernier portions formed on a SOI substrate, which comprises the step of removing semiconductor layer portions corresponding to the alignment mark portions and/or the vernier portions. In further another aspect of the invention, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a new pattern of a strage node formed longitudinally along a word line. Further, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a unique storage node having a conductive side wall.

Abstract: A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.

Abstract: A method for manufacture of a full CMOS type SRAM, comprising the steps of forming a first mask layer on a semiconductor layer, and patterning the first mask layer by photolithography to form semiconductor island layers where a driver MOS transistor and a load MOS transistor are formable with a slight space therebetween; forming a second mask layer on the semiconductor layer, and patterning the second mask layer by photolithography in such a manner as to overlap the region with one of the driver and load MOS transistors, but not to overlap the isolating region between the transistors; masking, with a resist film, the region with the other of the driver and load MOS transistors, and etching the first mask layer while masking the same with the resist film and the second mask layer; and etching the semiconductor layer while masking the same with the first mask layer, thereby forming mutually isolated semiconductor island layers where the driver and load MOS transistors are formed respectively.

Abstract: A method for manufacture of a full CMOS type SRAM, comprising the steps of forming a first mask layer on a semiconductor layer, and patterning the first mask layer by photolithography to form semiconductor island layers where a driver MOS transistor and a load MOS transistor are formable with a slight space therebetween; forming a second mask layer on the semiconductor layer, and patterning the second mask layer by photolithography in such a manner as to overlap the region with one of the driver and load MOS transistors, but not to overlap the isolating region between the transistors; masking, with a resist film, the region with the other of the driver and load MOS transistors, and etching the first mask layer while masking the same with the resist film and the second mask layer; and etching the semiconductor layer while masking the same with the first mask layer, thereby forming mutually isolated semiconductor island layers where the driver and load MOS transistors are formed respectively.

Abstract: A semiconductor memory device including an address decode signal transmission circuit comprising address buffers; a predecoder; address buses provided before a main decode; a transmission circuit for outputting predecoded signals to the address buses while limiting amplitude thereof; and a receiving circuit provided before the main decoder for differentially amplifying signals from the address buses, wherein the memory cell array is divided into a plural number of sub-blocks and power can be selectively supplied to at least one of the sub-blocks.

Abstract: There is disclosed a magnetic head which can be used for various magnetic disk drives and easily and economically fabricated. The head comprises a magnetic core consisting of a ferrite. The core is composed of two parts bonded together with a glass. A gap, a magnetic metal film, and an intermediate film are formed between the two parts of the core. The intermediate film is formed of the same glass as said glass by sputtering and has a thickness between 30 and 150 .ANG.. The metal film has a thickness between 1 and 10 .mu.m. The glass consists mainly of SiO.sub.2, for example.

Abstract: The present invention is directed to a MIS semiconductor device having a semiconductor layer formed on an insulating substrate and a gate electrode formed on this semiconductor layer through a gate insulating film, which is provided with a semiconductor region of a second conductivity type or a metal layer formed adjacent to a source region of a first conductivity type but separated from a channel region, thereby suppressing degradation of breakdown voltage caused by impact ionization, which is a defect of the MIS semiconductor device formed on an SOI substrate, to improve the reliability of this kind of MIS semiconductor devices.

Abstract: An indicating apparatus of a camera having a camera body which has an indicating portion in which information on the camera is indicated. The indicating portion includes a main indicating portion, which generally indicates the information on the camera, and an enlarged indicating portion, which enlarges and indicates specific information indicated in the main indicating portion.

Abstract: A thin film MOS transistor has a construction which can minimize scattering of electron and thus maximize electrons mobility for allowing higher speed operation of the transistor. For this, the MOS transistor has a thin film semiconductor layer having a thickness in a range less than or equal to 100 nm, between a pair of gate electrodes which oppose each other across the semiconductor layer.

Abstract: A semiconductor memory having storage cells each consisting of a MIS transistor and a capacitor, and a method of manufacturing the same. The semiconductor memory comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and semiconductor regions formed on the surface of the insulating layer. The semiconductor memory is characterized in that the MIS transistors are formed, respectively, on the surfaces of the semiconductor regions and separated from each other and from the semiconductor substrate by an insulating layer, and the capacitors are formed, respectively, under the corresponding MIS transistors. The insulating layer separating the MIS transistors from each other and from the semiconductor substrate reduces current leakage between the storage cells and reduces capacitance across bit lines formed on the side of the MIS transistors and the semiconductor substrate.