Abstract: A thin film MOS transistor has a construction which can minimize scattering of electron and thus maximize electrons mobility for allowing higher speed operation of the transistor. For this, the MOS transistor has a thin film semiconductor layer having a thickness in a range less than or equal to 100 nm, between a pair of gate electrodes which oppose each other across the semiconductor layer.

Abstract: A semiconductor memory having storage cells each consisting of a MIS transistor and a capacitor, and a method of manufacturing the same. The semiconductor memory comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and semiconductor regions formed on the surface of the insulating layer. The semiconductor memory is characterized in that the MIS transistors are formed, respectively, on the surfaces of the semiconductor regions and separated from each other and from the semiconductor substrate by an insulating layer, and the capacitors are formed, respectively, under the corresponding MIS transistors. The insulating layer separating the MIS transistors from each other and from the semiconductor substrate reduces current leakage between the storage cells and reduces capacitance across bit lines formed on the side of the MIS transistors and the semiconductor substrate.

Abstract: The present invention relates to a method for polishing a silicon wafer. The method comprises the steps of: (a) supplying a polishing fluid to a polishing surface, the polishing fluid including an alkaline fluid and polishing particles of high-purity silica dispersed in the alkaline fluid, the polishing surface being planar; (b) bringing a silicon wafer in contact with the polishing surface; and (c) moving at least one of the silicon wafer and the polishing surface relative to the other, thereby polishing the silicon wafer. The method is characterized by the following: the polishing surface is made of a ceramic material harder than the silicon wafer and more resistant to mechanochemical polishing than silicon, and the maximum roughness of the ceramic is less than 0.02 .mu.m.

Abstract: A method for manufacture of a semiconductor wafer in a manner to attain a high uniformity in the thickness of a semiconductor layer, by first forming hardly polishable stoppers of mutually different thicknesses in the semiconductor, then polishing the semiconductor until the thicker stopper is exposed on one main surface of the semiconductor, subsequently removing the thicker stopper to attain a thickness less than that of the thinner stopper, and thereafter polishing the aforesaid one main surface of the semiconductor until the thinner stopper is exposed. There is also disclosed a semiconductor device of a quantum well wire structure comprising a semiconductor layer formed on an insulator substrate, a thermally oxidized film of the semiconductor layer formed on such layer, and a gate electrode fromed on one side of the semiconductor layer, wherein the channel width is determined by the thickness of the semiconductor layer.

Abstract: The present invention relates to a semiconductor device in which a semiconductor element is formed on a semiconductor layer (3) supported on a substrate (1) via at least insulating layers (2) and (4) as shown in FIGS. 1 and 2 and a method of fabricating the same. The semiconductor layer (3) has wiring layers (5) and (6) on both surfaces thereof, thus leading itself well for increasing the density of wiring and for increasing the operation speed in a large-scale integrated circuit device.

Abstract: A semiconductor memory device having a number of memory cells. Each of the memory cells comprises a diode having a first electrode connected to a bit line. The diode has a second electrode connected at a point to one terminal of a storage capacitor, the other terminal of which is connected to a word line. A reset circuit is provided for resetting the point to a predetermined potential.

Abstract: A data processing system is provided which includes ALU data busses, temporary operand storage registers, an accumulator, and a set of latches for temporarily storing data to be supplied to the input of the ALU. Output multiplexer is provided which can select the output of one of the latches or that of the ALU which is sent to the accumulator. A detector is also provided for determining whether the smaller or larger one of two data elements is stored in said latches according to the status of the ALU and a new MIN/MAX instruction and the selected data element is returned to a predetermined temporary storage register via the output multiplexer. A controller operates in cooperation with the system instruction decoder to effect this operation with a single machine instruction.

Abstract: First and second gate-controlled switches are connected analogously to a Darlington transistor pair with a slow-response diode connected to delay application of a turn-off signal to the second gate-controlled switch until the first gate-controlled switch is fully turned OFF. The Darlington-type connection reduces a drive current required from a driving source to maintain the second gate-controlled switch fully ON for passing a load current therethrough.

Abstract: A semiconductor device includes a semiconductor substrate, a first region of first conductivity type in the substrate, a second region of second conductivity type in the substrate and adjacent to the first region, a third region of the first conductivity type adjacent to the second region having at least a portion on the substrate which is comprised of the same element as the substrate and oxygen, the band gap energy of the portion being larger than that of the second region and means for transporting majority carriers in the first region to the third region.

Abstract: A replaceable gang head machine tool unit having a driving motor, the unit being mounted on a slide table arranged to be driven and advance in a given direction wherein: there is provided an annular rail comprising a rear stationary rail and a front movable rail disposed on a machine base, a plurality of gang heads disposed around the annular rail and supported thereon, the plurality of gang heads being arranged to be rotated on the annular rail by an index table to permit any desired gang head to be selected therefrom on the movable rail. When the working unit is in a retreated position in the machine base, the selected head on the movable rail may be joined to the unit for travel therewith together with the movable rail.

Abstract: A method of an iron Fe ion implantation into a semiconductor substrate of an N-type conductivity is disclosed. The method comprises the steps of implanting Fe ions into an N-type semiconductor substrate from its one surface with the dose amount of 10.sup.10 to 10.sup.15 cm.sup.-2 and heat-treating the semiconductor substrate with Fe ions at 850.degree. to 1250.degree. C. to control the lifetime of the minority carrier in the substrate and hence to reduce the temperature dependency of the lifetime.

Abstract: A polycrystalline layer is formed as a passivation layer on a monocrystalline semiconductor substrate, the polycrystalline layer containing oxygen in the range between 2 to 45 atomic percent. The density of surface states between the surface of said substrate and the polycrystalline silicon layer is less than 10.sup.10 /cm.sup.2 .multidot.eV at the middle portion of a forbidden band, and the interface density of fixed charge in the polycrystalline layer is less than 10.sup.10 /cm.sup.2.

Abstract: An oxygen or nitrogen ion beam is implanted into a polycrystalline silicon or in an amorphous silicon layer, or a single crystal device body or layer, on a semiconductor substrate to an extent sufficient to convert the polycrystalline silicon layer, the amorphous layer or the single crystal device body or layer into a semi-insulating layer having a resistivity of 10.sup.7 to 10.sup.11 ohm-cm, which has improved passivation property.

Abstract: Silicon ions are implanted in a silicon dioxide layer on a silicon substrate so that the dioxide layer is converted into a semi-insulating layer having an improved passivation property.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first polycrystalline silicon layer containing oxygen atoms on a semiconductor layer, of forming a second polycrystalline silicon layer containing nitrogen atoms on the first polycrystalline silicon layer, of removing a predetermined part of the first and second polycrystalline silicon layers to form an opening therein, and of diffusing impurity material into the semiconductor layer through the opening in order to form a diffused region. The fabricating process can be remarkably simplified.

Abstract: A semiconductive device is provided which includes a single crystal substrate. A first insulating layer arranged on one surface of the substrate is of polycrystalline silicon containing oxygen. A second insulating layer formed on the first insulating layer is of polycrystalline silicon containing one of a group consisting of nitrogen, Si.sub.3 N.sub.4, Al.sub.2 O.sub.3 and silicone resin. The substrate includes at least one PN junction which extends to the said surface of the substrate. A novel method of making is also disclosed.

Abstract: A semiconductor device comprising a silicon substrate with an oxygen doped polycrystalline or amorphous silicon layer formed on the substrate so as to form a hetero junction therewith. A transistor formed according to the invention has an emitter-base hetero junction and has a high current gain.

Abstract: A semiconductor photovoltaic device is comprised of 2n layers of alternating p-type and n-type material having respective PN junctions between adjacent layers, wherein n is an integer greater than 1. Each layer has a thickness which is less than the diffusion length of a minority carrier therein. The PN junctions are excited by light which is incident on the device to thereby cause majority carriers to be accumulated in the respective layers so as to forward bias all of the PN junctions. As a result of this forward biasing, minority carriers are injected across a first PN junction fr0m one layer into an adjacent layer and then traverse the next PN junction into the next succeeding layer. The photovoltaic device thus is adapted to supply a voltage and a current to a load.