Patents by Inventor Takeshi Takagi

Takeshi Takagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180006089
    Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 4, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Natsuki FUKUDA, Mutsumi OKAJIMA, Atsushi OGA, Toshiharu TANAKA, Takeshi YAMAGUCHI, Takeshi TAKAGI, Masanori KOMURA
  • Patent number: 9829521
    Abstract: An estimation method for a variable resistance element including (i) a first electrode, (ii) a second electrode, and therebetween (iii) a variable resistance layer in which a local region is formed which has resistive status that reversibly changes according to an electric pulse applied between the first electrode and the second electrode, the estimation method including: obtaining, when changes are made to the resistive status of the local region, measurement values each indicating a resistance state after one of the changes; and determining, based on a distribution of the obtained measurement values, an estimated amount of a physical parameter regarding structural characteristics of the local region by a calculation.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: November 28, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Zhiqiang Wei, Takeki Ninomiya, Shunsaku Muraoka, Takeshi Takagi
  • Patent number: 9812507
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate which extends in first and second directions; first wiring lines which are arranged in a third direction, and which extend in the first direction; second wiring lines which are arranged in the first direction and extend in the third direction; and memory cells disposed at intersections of the first wiring lines and the second wiring lines, one of the memory cells including a first film and a second film whose permittivity is different from that of the first film which are stacked in the second direction between one of the first wiring lines and one of the second wiring lines, and the second films of two of the memory cells adjacent in the third direction being separated between the two memory cells.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: November 7, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masanori Komura, Takeshi Takagi
  • Publication number: 20170307571
    Abstract: A liquid chromatography measurement method includes: switching between a first measurement mode using a liquid chromatography method in which hemoglobin A1c and a hemoglobin variant are measured in a measurement sample by sequentially delivering a first component-separating eluent, a second component-separating eluent and a wash eluent to an analytical column, and a second measurement mode using the liquid chromatography method in which the hemoglobin A1c is measured by sequentially delivering the first component-separating eluent and the wash eluent to the analytical column; delivering the wash eluent in the first measurement mode prior to an influence from the second component-separating eluent disappearing such that a first retention time of the hemoglobin A1c in the first measurement mode and a second retention time of the hemoglobin A1c in the second measurement mode are substantially the same as each other; and delivering the first component-separating eluent after the wash eluent.
    Type: Application
    Filed: April 18, 2017
    Publication date: October 26, 2017
    Applicant: ARKRAY, Inc.
    Inventors: Akira SEZAKI, Takeshi TAKAGI
  • Patent number: 9768233
    Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body facing the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a lower surface of the projecting part contacting an upper surface of the one of the first conductive films.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: September 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Natsuki Fukuda, Mutsumi Okajima, Atsushi Oga, Toshiharu Tanaka, Takeshi Yamaguchi, Takeshi Takagi, Masanori Komura
  • Publication number: 20170263682
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate which extends in first and second directions; first wiring lines which are arranged in a third direction, and which extend in the first direction; second wiring lines which are arranged in the first direction and extend in the third direction; and memory cells disposed at intersections of the first wiring lines and the second wiring lines, one of the memory cells including a first film and a second film whose permittivity is different from that of the first film which are stacked in the second direction between one of the first wiring lines and one of the second wiring lines, and the second films of two of the memory cells adjacent in the third direction being separated between the two memory cells.
    Type: Application
    Filed: August 3, 2016
    Publication date: September 14, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masanori KOMURA, Takeshi TAKAGI
  • Publication number: 20170256588
    Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body facing the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a lower surface of the projecting part contacting an upper surface of the one of the first conductive films.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 7, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Natsuki FUKUDA, Mutsumi OKAJIMA, Atsushi OGA, Toshiharu TANAKA, Takeshi YAMAGUCHI, Takeshi TAKAGI, Masanori KOMURA
  • Patent number: 9728585
    Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor substrate which extends in first and second directions that intersect each other; a plurality of first wiring lines which are arranged in a third direction that intersects the first direction and the second direction, and which extend in the first direction; a plurality of second wiring lines which are arranged in the first direction and extend in the third direction; and a plurality of memory cells disposed at intersections of the first wiring lines and the second wiring lines, one of the memory cells having a first film whose resistance changes electrically, a thickness in the second direction of the first film changing with respect to a change of position in the third direction, and the first films of two of the memory cells adjacent in the third direction being separated between the two memory cells.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: August 8, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaki Yamato, Takeshi Yamaguchi, Takeshi Takagi, Natsuki Fukuda
  • Patent number: 9711721
    Abstract: According to one embodiment, a plurality of first wirings are disposed in a first direction and a second direction which intersect with each other, and extended in a third direction. A second wiring stack is configured to include second wirings and interlayer insulating films which are extended and alternately stacked in the second direction. A memory cell includes, in the first direction, a first variable resistive layer which is disposed on a side near the first wiring and a second variable resistive layer which is disposed on a side near the second wiring. The second variable resistive layer is disposed between the interlayer insulating films in the third direction, and made of a material which is obtained by oxidizing the second wiring.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: July 18, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Takagi, Takeshi Yamaguchi
  • Publication number: 20170117039
    Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises: a memory cell array; and a control circuit that manages a setting operation and a read operation. The memory cell array comprises: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell including a variable resistance element and a nonlinear element. The variable resistance element is configured having a first metal film, a first variable resistance film, a second variable resistance film, and a second metal film stacked and disposed therein in this order. A work function of the second metal film is smaller than a work function of the first metal film.
    Type: Application
    Filed: March 15, 2016
    Publication date: April 27, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaki YAMATO, Takeshi YAMAGUCHI, Takeshi TAKAGI, Hiroyuki ODE, Toshiharu TANAKA
  • Publication number: 20170110847
    Abstract: An optical fiber laser device generates laser light by using an optical amplifying fiber as an amplification medium in a laser oscillator and includes: an optical outputting fiber configured to emit laser light to an outside; a return-light-attenuating portion configured to perform an attenuation process to return light propagating through at least the optical outputting fiber in a reverse direction of the laser light; a thermal conversion unit provided at the return-light-attenuating portion and configured to convert the return light into heat; a temperature-monitoring device configured to measure an increase in a temperature, of the return-light-attenuating portion, caused by the heat converted by the thermal conversion unit; and a control unit configured to decrease or stop an output of the laser light when the temperature measured by the temperature-monitoring device becomes a predetermined threshold temperature or higher.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 20, 2017
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Koji KAJIWARA, Takeshi TAKAGI, Kousuke KASHIWAGI, Kazuaki HYUGA, Yoshihiro EMORI
  • Publication number: 20170062713
    Abstract: According to one embodiment, A memory device includes a pillar, a first wiring, a second wiring, an insulating film provided between the first wiring and the second wiring, a first layer provided between the first wiring and the pillar in the second direction and including a first metal oxide containing a first metal and oxygen, a second layer provided between the second wiring and the pillar in the second direction and including the first metal oxide containing the first metal and oxygen, and an intermediate film provided between the pillar and the first layer and between the pillar and the second layer in the second direction and including a second metal oxide containing the first metal and oxygen. Concentration of oxygen contained in the first metal oxide is lower than concentration of oxygen contained in the second metal oxide.
    Type: Application
    Filed: February 2, 2016
    Publication date: March 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi TAKAGI, Takeshi YAMAGUCHI, Masaki YAMATO, Hiroyuki ODE, Toshiharu TANAKA
  • Patent number: 9559300
    Abstract: In accordance with an embodiment, a resistive random access memory device includes a substrate, first and second wiring lines, and a storage cell. The first and second wiring lines are disposed on the substrate so as to intersect each other. The storage cell is disposed between the first and second wiring lines at the intersection of the first and second wiring lines and includes a first electrode, a resistive switching film on the first electrode, a second electrode on the resistive switching film, and a tantalum oxide (TaOx) layer. The first electrode is electrically connected to the first wiring line. The second electrode is electrically connected to the second wiring line. The tantalum oxide (TaOx) layer is disposed between the first electrode and the resistive switching film and is in contact with the resistive switching film.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: January 31, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki Ode, Takeshi Yamaguchi, Takeshi Takagi, Toshiharu Tanaka, Masaki Yamato
  • Publication number: 20170025475
    Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the first direction and a resistance change film provided between the first wiring and the second wiring. The second wiring includes a first conductive layer and a first intermediate layer including a first region provided between the first conductive layer and the resistance change film. The first intermediate layer includes a material having nonlinear resistance characteristics.
    Type: Application
    Filed: February 8, 2016
    Publication date: January 26, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi TAKAGI, Takeshi YAMAGUCHI, Masaki YAMATO, Hiroyuki ODE, Toshiharu TANAKA
  • Publication number: 20160325524
    Abstract: A laminated structure has a first layer formed from a fiber reinforced plastic, a second layer formed from a fiber reinforced plastic and arranged opposed to the first layer, a first core layer formed from a first resin foam and arranged between the first layer and the second layer, and a second core layer formed from a second resin foam and arranged between the first core later and the second layer. The first resin foam has a higher flame resistance than the second resin foam. A laminated structure having flame resistance and high strength enough to endure a bird strike or the like at the same time can be manufactured at relatively low manufacturing cost.
    Type: Application
    Filed: December 19, 2014
    Publication date: November 10, 2016
    Applicant: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Ryo MORIHASHI, Takeshi HASEGAWA, Yosuke TSUMURA, Takeshi TAKAGI
  • Publication number: 20160260479
    Abstract: A semiconductor memory device comprises: a memory cell array 11; and a control circuit 16 that controls a voltage applied to the memory cell array 11. The memory cell array 11 includes: a plurality of word lines WL and bit lines BL that intersect each other; and a memory cell MC disposed at each of intersections of these word lines WL and bit lines BL. The memory cell MC includes a variable resistance element VR and a non-ohmic element NO. The variable resistance element VR is formed by a hafnium oxide crystalline film of monoclinic crystal in which a proportion of a component oriented in a (?1, 1, 1) plane and a (1, 1, 1) plane is 90% or more. This hafnium oxide crystalline film can be manufactured by a film-forming process by atomic layer deposition, employing an inorganic type hafnium precursor.
    Type: Application
    Filed: September 3, 2015
    Publication date: September 8, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuiki ODE, Takeshi YAMAGUCHI, Takeshi TAKAGI, Toshiharu TANAKA, Masaki YAMATO
  • Patent number: 9429579
    Abstract: The present invention relates to a blood analysis apparatus X for measuring concentrations of glucose and glycohemoglobin in blood. The blood analysis apparatus X is configured to perform the concentration measurement of the glucose and the glycohemoglobin by one sampling of blood 13. The blood analysis apparatus X is preferably configured to simultaneously carry out sample preparations for concentration measurement of the glucose and the glycohemoglobin by one sample preparation. The blood analysis apparatus X may be configured to perform dilution of a blood sample for measuring the glycohemoglobin and dilution of a blood sample for measuring the glucose using the same diluent.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: August 30, 2016
    Assignee: ARKRAY, INC.
    Inventors: Koji Sugiyama, Tatsuo Kamata, Takeshi Takagi
  • Patent number: 9418737
    Abstract: A nonvolatile semiconductor memory device includes: a memory cell array; and a control circuit that controls a voltage applied to this memory cell array. The memory cell array includes: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell disposed at an intersection of these lines and including a variable resistance element. In a rewrite operation of the memory cell, the control circuit repeatedly perform a pulse application operation and a verify operation, the pulse application operation applying a pulse voltage to the memory cell, and the verify operation applying a first voltage to the memory cell to determine whether the rewrite operation has been completed or not. The control circuit is configured to, in a read operation from the memory cell, apply a second voltage to the memory cell. The second voltage has a voltage value larger than the first voltage.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: August 16, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi Takagi, Masaki Yamato, Hiroyuki Ode, Takeshi Yamaguchi, Toshiharu Tanaka
  • Patent number: 9390797
    Abstract: A method of driving a variable resistance element comprises: before a first write step is performed, applying an initial voltage pulse of a first polarity to change a resistance value of a metal oxide layer from a resistance value corresponding to an initial state of the metal oxide layer to another resistance value; wherein when the resistance value corresponding to the initial state is R0, the resistance value corresponding to a write state is RL, the resistance value corresponding to an erase state is RH, another resistance value is R2, a maximum value of the current flowing when the initial voltage pulse is applied is IbRL, a maximum value of the current flowing when the write voltage pulse is applied is IRL, and a maximum value of the current flowing when the erase voltage pulse is applied is IRH, R0>RH>R2?RL, and |IRL|>|IbRL| are satisfied.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: July 12, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shunsaku Muraoka, Satoru Mitani, Takeshi Takagi, Koji Katayama
  • Publication number: 20160189776
    Abstract: A nonvolatile semiconductor memory device includes: a memory cell array; and a control circuit that controls a voltage applied to this memory cell array. The memory cell array includes: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell disposed at an intersection of these lines and including a variable resistance element. In a rewrite operation of the memory cell, the control circuit repeatedly perform a pulse application operation and a verify operation, the pulse application operation applying a pulse voltage to the memory cell, and the verify operation applying a first voltage to the memory cell to determine whether the rewrite operation has been completed or not. The control circuit is configured to, in a read operation from the memory cell, apply a second voltage to the memory cell. The second voltage has a voltage value larger than the first voltage.
    Type: Application
    Filed: July 30, 2015
    Publication date: June 30, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi TAKAGI, Masaki YAMATO, Hiroyuki ODE, Takeshi YAMAGUCHI, Toshiharu TANAKA