Patents by Inventor Takeshi Takagi

Takeshi Takagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8535510
    Abstract: This invention provides a substrate concentration measuring method for measuring a concentration of a substrate included in a specimen based on an output for measurement from an enzyme electrode when the enzyme electrode and the substrate are reacted with each other, the substrate concentration is calculated using an output for correction from the enzyme electrode obtained when a reference solution whose substrate concentration is known and the enzyme electrode are reacted with each other before or after the enzyme electrode and the substrate are reacted with each other. For example, the output for correction is measured by each specimen. In this method, the substrate concentration may be calculated using the output for correction for the specimen to be measured and an output for correction corresponding to the at least one other specimen and measured prior to the output for correction.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: September 17, 2013
    Assignee: Arkray, Inc.
    Inventors: Tatsuo Kamata, Takeshi Takagi, Yuki Ito
  • Patent number: 8531869
    Abstract: A resistance variable layer changes: to a second resistance state in such a manner that its resistance value stops decreasing when an interelectrode voltage reaches a negative first voltage; to a first resistance state in such a manner that its resistance value starts increasing when the interelectrode voltage reaches a positive second voltage which is equal in absolute value to the first voltage; to the first resistance state in such a manner that the resistance variable layer flows an interelectrode current such that the interelectrode voltage is maintained at a third voltage higher than the second voltage, when the interelectrode voltage reaches the third voltage; and to the first resistance state in such a manner that its resistance value stops increasing when the interelectrode current reaches a first current in a state where the interelectrode voltage is not lower than the second voltage and lower than the third voltage.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: September 10, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoshikazu Katoh, Shunsaku Muraoka, Takeshi Takagi
  • Publication number: 20130223131
    Abstract: A driving method for driving a variable resistance element and a nonvolatile memory device, which achieves stable storage operation. In a low resistance write process, a low resistance writing voltage pulse having the negative polarity is applied once to a variable resistance layer included in a variable resistance element while in a high resistance write process, a high resistance writing voltage pulse having the positive polarity is applied more than twice to the same variable resistance layer. Here, when a voltage value of one of the high resistance writing voltage pulses is VH1 and a voltage value of the other high resistance writing voltage pulse applied subsequently is VH2, VH1>VH2 is satisfied.
    Type: Application
    Filed: June 11, 2012
    Publication date: August 29, 2013
    Inventors: Takeshi Takagi, Koji Katayama
  • Patent number: 8508976
    Abstract: Provided is a nonvolatile memory element which has a small variation in operation and allow stable operation. The nonvolatile memory element includes: a first electrode (102); a second electrode (106); a variable resistance layer (105) which is formed between the electrodes (102 and 106) and is connected to the electrodes (102 and 106), and which reversibly changes between a high resistance state and a low resistance state according to a polarity of a voltage applied between the electrodes (102 and 106); and a fixed resistance layer (104) which has a resistance value that is 0.1 and 10 times as large as a resistance value of the variable resistance layer in the high resistance state, the fixed resistance layer (104) being formed between the electrodes (102 and 106) and being electrically connected to at least a part of the variable resistance layer (105).
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: August 13, 2013
    Assignee: Panasonic Corporation
    Inventors: Koji Katayama, Takeshi Takagi
  • Patent number: 8486788
    Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: July 16, 2013
    Assignee: Panasonic Corporation
    Inventors: Junko Iwanaga, Takeshi Takagi, Yoshihiko Kanzawa, Haruyuki Sorada, Tohru Saitoh, Takahiro Kawashima
  • Publication number: 20130178042
    Abstract: Provided is a method for manufacturing a variable resistance element, the method including: forming a first electrode material layer above a substrate; forming a first tantalum oxide material layer; forming a second tantalum oxide material layer; forming a second electrode material layer; and annealing at least the first tantalum oxide material layer after forming the first tantalum oxide material layer and before forming the second electrode material layer, wherein an oxygen content percentage of one of the first tantalum oxide material layer and the second tantalum oxide material layer is higher than an oxygen content percentage of the other.
    Type: Application
    Filed: January 30, 2012
    Publication date: July 11, 2013
    Inventors: Takeki Ninomiya, Yukio Hayakawa, Takumi Mikawa, Takeshi Takagi
  • Patent number: 8454823
    Abstract: A sample stirring device of the present invention includes a driving roller and two follower rollers for coming into contact with a sample container including a cylindrical portion for containing a sample to be stirred. The driving roller is driven for rotation to stir the sample contained in the sample container. The two follower rollers have rotation axes inclined with respect to an axial direction of the cylindrical portion. This arrangement allows the sample container such as a blood collection tube to be rotated stably.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: June 4, 2013
    Assignee: Arkray, Inc.
    Inventors: Shin-ichi Oota, Hidenari Yamagata, Takeshi Takagi, Koji Egawa
  • Patent number: 8445885
    Abstract: A nonvolatile memory element includes first and second electrodes, and a resistance variable layer disposed therebetween. At least one of the first and second electrodes includes a platinum-containing layer. The resistance variable layer includes a first oxygen-deficient transition metal oxide layer which is not physically in contact with the platinum-containing layer and a second oxygen-deficient transition metal oxide layer which is disposed between the first oxygen-deficient transition metal oxide layer and the platinum-containing layer and is physically in contact with the platinum-containing layer. When oxygen-deficient transition metal oxides included in the first and second oxygen-deficient transition metal oxide layers are expressed as MOx, and MOy, respectively, x<y is satisfied. The platinum-containing layer has a thickness which is not less than 1 nm and not more than 23 nm.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: May 21, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoshihiko Kanzawa, Satoru Mitani, Zhiqiang Wei, Takeshi Takagi, Koji Katayama
  • Patent number: 8445319
    Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0<x<2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x<y<2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: May 21, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoshihiko Kanzawa, Koji Katayama, Satoru Fujii, Shunsaku Muraoka, Koichi Osano, Satoru Mitani, Ryoko Miyanaga, Takeshi Takagi, Kazuhiko Shimakawa
  • Publication number: 20130112936
    Abstract: A variable resistance element including: a first electrode; a second electrode; and a variable resistance layer having a resistance value which reversibly changes according to electrical signals applied, wherein the variable resistance layer includes a first variable resistance layer comprising a first oxygen-deficient transition metal oxide, and a second variable resistance layer comprising a second transition metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first transition metal oxide layer, the second electrode has a single needle-shaped part at the interface with the second variable resistance layer, and the second variable resistance layer is interposed between the first variable resistance layer and the second electrode, is in contact with the first variable resistance layer and the second electrode, and covers the needle-shaped part.
    Type: Application
    Filed: January 18, 2012
    Publication date: May 9, 2013
    Applicant: Panasonic Corporation
    Inventors: Zhiqiang WEI, Takeshi Takagi, Satoru Mitani, Yoshio Kawashima, Ichirou Takahashi
  • Patent number: 8432721
    Abstract: Programming a variable resistance element includes: a writing step of applying a writing voltage pulse to transition metal oxide comprising two stacked metal oxide layers to decrease resistance of the metal oxide, each metal oxide layer having different oxygen deficiency; and an erasing step of applying an erasing voltage pulse, of different polarity than the writing pulse, to the metal oxide to increase resistance of the metal oxide. |Vw1|>|Vw2|, Vw1 representing voltage of the writing pulse for first to N-th writing steps, and Vw2 representing voltage of the writing pulse for (N+1)-th and subsequent writing steps, N being at least equal to 1, te1>te2, te1 representing pulse width of the erasing pulse for first to M-th erasing steps, and te2 representing pulse width of the erasing pulse for (M+1)-th and subsequent erasing steps. M>1. The (N+1)-th writing step follows the M-th erasing step.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: April 30, 2013
    Assignee: Panasonic Corporation
    Inventors: Mitsuteru Iijima, Takeshi Takagi
  • Publication number: 20130082230
    Abstract: A variable resistance nonvolatile memory element manufacturing method includes: forming a first electrode on a substrate; forming a first metal oxide layer having a predetermined oxygen content atomic percentage on the first electrode; forming, in at least one part of the first metal oxide layer, a modified layer higher in resistance than the first metal oxide layer, by oxygen deficiency reduction; forming a second metal oxide layer lower in oxygen content atomic percentage than the first metal oxide layer, on the modified layer; and forming a second electrode on the second metal oxide layer. A variable resistance layer includes the first metal oxide layer having the modified layer and the second metal oxide layer, connects to the first electrode and the second electrode, and changes between high and low resistance states according to electrical pulse polarity.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Inventors: Koji Katayama, Takeshi Takagi
  • Patent number: 8406035
    Abstract: A resistance variable layer has a characteristic in which the resistance variable layer changes to a second resistance state (RL) in such a manner that its resistance value stops decreasing when an interelectrode voltage reaches a first voltage (V1) which is a negative voltage, the resistance variable layer changes to a first resistance state (RH) in such a manner that its resistance value starts increasing when the interelectrode voltage reaches a second voltage (V2) which is a positive voltage which is equal in absolute value to the first voltage, the resistance variable layer changes to the first resistance state in such a manner that the resistance variable layer flows an interelectrode current such that the interelectrode voltage is maintained at a third voltage (V3) higher than the second voltage, when the interelectrode voltage reaches the third voltage, and the resistance variable layer changes to the first resistance state in such a manner that its resistance value stops increasing when the interelec
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: March 26, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoshikazu Katoh, Shunsaku Muraoka, Takeshi Takagi
  • Patent number: 8405076
    Abstract: A nonvolatile memory element (100) includes a variable resistance layer (107) including a first metal oxide MOx and a second metal oxide MOy, and reaction energy of chemical reaction related to the first metal oxide, the second metal oxide, oxygen ions, and electrons is 2 eV or less. The chemical reaction is expressed by a formula 13, where a combination (MOx, MOy) of MOx and MOy is selected from a group including (Cr2O3, CrO3), (Co3O4, Co2O3), (Mn3O4, Mn2O3), (VO2, V2O5), (Ce2O3, CeO2), (W3O8, WO3), (Cu2O, CuO), (SnO, SnO2), (NbO2, Nb2O5), and (Ti2O3, TiO2).
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: March 26, 2013
    Assignee: Panasonic Corporation
    Inventors: Takeki Ninomiya, Takeshi Takagi, Zhiqiang Wei
  • Patent number: 8395930
    Abstract: A method includes applying a first polarity writing voltage pulse to a metal oxide layer to change its resistance state from high to low into a write state, applying a second polarity erasing voltage pulse different from the first polarity to the metal oxide layer to change its resistance state from low to high into an erase state, and applying an initial voltage pulse having the second polarity to the metal oxide layer before first application of the writing voltage pulse, to change an initial resistance value of the metal oxide layer. R0>RH>RL and |V0|>|Ve|?|Vw| are satisfied where R0, RL, and RH are the resistance values of the initial, write, and erase states, respectively, of the metal oxide layer, and V0, Vw, and Ve are voltage values of the initial, writing, and erasing voltage pulses, respectively.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: March 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Shunsaku Muraoka, Takeshi Takagi, Satoru Mitani, Koji Katayama
  • Patent number: 8391051
    Abstract: Provided is a programming method for improving the retention characteristics of information in a variable resistance nonvolatile memory element. The method includes: a first writing process of applying a first voltage V1 having a first polarity to set the variable resistance nonvolatile storage element to a low resistance state LR indicating first logic information (S01); a second writing process of applying a second voltage V2 having a second polarity different from the first polarity to set the variable resistance nonvolatile storage element to a first high resistance state HR1 (S02); and a partial write process of applying a third voltage V3 having the first polarity so as to set the variable resistance layer to a second high resistance state HR2 indicating second logic information different from the first logic information (S05). Here, |V3|<|V1|, and resistance values in HR1, HR2, LR are greater in this order.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: March 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoshihiko Kanzawa, Takeshi Takagi
  • Publication number: 20130037775
    Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (108); a resistance variable layer (107) which is interposed between the first electrode (103) and the second electrode (107) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes (103) and (108), and the resistance variable layer (107) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfOx (0.9?x?1.6), and a second hafnium-containing layer having a composition expressed as HfOy (1.8?y?2.0) are stacked together.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 14, 2013
    Inventors: Satoru Mitani, Yoshihiko Kanzawa, Koji Katayama, Takeshi Takagi
  • Publication number: 20130029469
    Abstract: A nonvolatile semiconductor memory apparatus including a substrate, lower-layer electrode wires provided on the substrate, an interlayer insulating layer provided with contact holes at locations respectively opposite to the lower-layer electrode wires, resistance variable layers which are respectively connected to the lower-layer electrode wires; and non-ohmic devices which are respectively provided on the resistance variable layers. The non-ohmic devices each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer.
    Type: Application
    Filed: July 31, 2012
    Publication date: January 31, 2013
    Inventors: Takumi MIKAWA, Takeshi TAKAGI
  • Publication number: 20130010522
    Abstract: A nonvolatile memory device (800) includes a variable resistance nonvolatile memory element (100) and a control circuit (810). The control circuit (810) determines whether a resistance value of the nonvolatile memory element (100) in a high resistance state is equal to or greater than a predetermined threshold value. Moreover, if the resistance value of the nonvolatile memory element (100) in the high resistance state is smaller than the threshold value, the control circuit (810) applies a first voltage (VL1) to the nonvolatile memory element (100) to change a resistance state of the nonvolatile memory element (100) from the high resistance state to the low resistance state.
    Type: Application
    Filed: October 26, 2011
    Publication date: January 10, 2013
    Inventors: Yoshihiko Kanzawa, Takeshi Takagi
  • Publication number: 20130010530
    Abstract: Provided is a method for driving a non-volatile memory element in which a variable resistance element including a first electrode, a second electrode, and a variable resistance layer capable of reversibly changing between a high resistance state and a low resistance state with application of electrical signals having different polarities is connected in series with a current steering element having bidirectional rectifying characteristics with respect to an applied voltage. After the non-volatile memory element is manufactured, the resistance value of the variable resistance layer is reduced from a resistance value in the initial resistance state higher than that in the high resistance state by applying, to the non-volatile memory element, a voltage pulse having the polarity identical to that of the voltage pulse for changing the variable resistance layer from the low resistance state to the high resistance state in the normal operations.
    Type: Application
    Filed: March 18, 2011
    Publication date: January 10, 2013
    Inventors: Koji Katayama, Takeshi Takagi, Mitsuteru Iijima