Abstract: A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.

Abstract: A liquid chromatography apparatus is provided with a sample preparation unit, a column that separates components of a sample, an eluent supplier that includes a feeder for supplying eluents to the column, a flow path directional valve capable of introducing fixed amounts of the sample and the eluents to the column, an analyzer for analyzing a test solution composed of the sample components separated by the column and one of the eluents, and a controller, wherein the eluent supplier supplies the eluents to the flow path directional valve in an unmixed state. As a result of employing this configuration, analysis time is shortened and eluent consumption is reduced.

Abstract: A method for programming a nonvolatile memory element includes: decreasing a resistance value of a variable resistance element in an initial state, by applying an initialization voltage pulse to a series circuit in which a load resistor having a first resistance value is connected in series with the variable resistance element and a MSM diode; applying, after the decreasing, a write voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a second resistance value lower than the first resistance value; and applying, after the decreasing, an erase voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a third resistance value lower than the first resistance value.

Abstract: A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.

Abstract: According to one embodiment, a plurality of first wirings is disposed in first and second directions crossing each other and extends in a third direction perpendicular to the first and second directions. Second wirings extend in the second direction and are provided at a predetermined interval in the third direction of the first wirings. The first wiring includes a metal plug layer and a barrier metal film. A standard electrode potential of a metal that forms the barrier metal film is higher than a standard electrode potential of a metal that forms the variable resistive layer.

Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (105), and a resistance variable layer (104) disposed between the first electrode (103) and the second electrode (104), a resistance value of the resistance variable layer varying reversibly according to an electric signal applied between the electrodes (103), (105), and the resistance variable layer (104) comprises at least a tantalum oxide, and is configured to satisfy 0<x<2.5 when the tantalum oxide is represented by TaOx.

Abstract: Provided is a method for driving a variable resistance nonvolatile storage element that can improve the information holding capability. The method includes: determining whether or not a current that flows through the nonvolatile storage element is larger than or equal to a first verify level IRL (Verify); determining whether or not a current that flows through the nonvolatile storage element is smaller than or equal to a second verify level IRH (Verify); and determining that the nonvolatile storage element is in the second resistance state when the current that flows through the nonvolatile storage element is smaller than a current reference level Iref, and determining that the nonvolatile storage element is in the first resistance state when the current is larger than the current reference level Iref, the current reference level Iref satisfying (IRL (Verify)+IRH (Verify))/2<Iref<IRL (Verify).

Abstract: A method for driving a nonvolatile memory element includes: a writing step of changing a variable resistance layer to a low resistance state, by applying a writing voltage pulse having a first polarity; and an erasing step of changing the variable resistance layer to a high resistance state, by applying an erasing voltage pulse having a second polarity different from the first polarity, wherein in the writing step, a first input and output terminal of a field effect transistor is a source terminal of the transistor, and when a pulse width of the writing voltage pulse is PWLR and a pulse width of the erasing voltage pulse is PWHR, PWLR and PWHR satisfy a relationship of PWLR<PWHR.

Abstract: Provided is a method for reading data from a variable resistance nonvolatile storage element, where the operation for reading data is less susceptible to a fluctuation phenomenon of resistance values in reading the data. The method includes: detecting a current value Iread that flows through the nonvolatile storage element that can be in a low resistance state RL and a high resistance state RH, with application of a fixed voltage; and determining that (i) the nonvolatile storage element is in a high resistance state when the current value Iread detected in the detecting is smaller than a current reference level Iref, and (ii) the nonvolatile storage element is in a low resistance state when the current value Iread detected in the detecting is larger than the reference level Iref, the current reference level Iref being defined by (IRL+IRH)/2<Iref<IRL.

Abstract: A variable resistance nonvolatile memory element includes: first and second electrode layers; a first variable resistance layer between the first and second electrode layers; and a second variable resistance layer between the second electrode layer and the first variable resistance layer and having a higher resistance value than the first variable resistance layer. When viewed in a direction perpendicular to the major surface of the second variable resistance layer, an outline of the second variable resistance layer is located inwardly of the outline of any one of the second electrode layer and the first variable resistance layer, and an outline of a face of the second variable resistance layer, the face being in contact with the first variable resistance layer is located inwardly of an outline of a face of the first variable resistance layer, the face being in contact with the second variable resistance layer.

Abstract: A driving method for driving a variable resistance element and a nonvolatile memory device, which achieves stable storage operation. In a low resistance write process, a low resistance writing voltage pulse having the negative polarity is applied once to a variable resistance layer included in a variable resistance element while in a high resistance write process, a high resistance writing voltage pulse having the positive polarity is applied more than twice to the same variable resistance layer. Here, when a voltage value of one of the high resistance writing voltage pulses is VH1 and a voltage value of the other high resistance writing voltage pulse applied subsequently is VH2, VH1>VH2 is satisfied.

Abstract: A memory device according to an embodiment, includes a selection element, a first interconnection provided in a first direction when viewed from the selection element and extending in the first direction, a plurality of second interconnections provided in a second direction crossing the first direction when viewed from the first interconnection and arranged in the first direction, a memory element provided between the first interconnection and the second interconnection, and a high resistance component connected between the selection element and the first interconnection and having a resistivity higher than a resistivity of the first interconnection and a resistivity of the second interconnection.

Abstract: According to one embodiment, a plurality of first wirings are arranged along a first direction and a second direction that intersect each other and extending in a third direction perpendicular to the first and second directions. A plurality of second wirings extend in the second direction and are provided at predetermined intervals along the third direction of the first wirings. N channel field-effect transistors are provided at ends of the first wirings. Memory cells are placed at intersections of the first wirings and the second wirings. The memory cells are formed of a variable resistive layer of which the first wiring side is large in resistivity and the second wiring side is small in resistivity.

Abstract: According to one embodiment, a plurality of first wirings are disposed in a first direction and a second direction which intersect with each other, and extended in a third direction. A second wiring stack is configured to include second wirings and interlayer insulating films which are extended and alternately stacked in the second direction. A memory cell includes, in the first direction, a first variable resistive layer which is disposed on a side near the first wiring and a second variable resistive layer which is disposed on a side near the second wiring. The second variable resistive layer is disposed between the interlayer insulating films in the third direction, and made of a material which is obtained by oxidizing the second wiring.

Abstract: According to one embodiment, a plurality of first wirings is disposed in first and second directions crossing each other and extends in a third direction perpendicular to the first and second directions. Second wirings extend in the second direction and are provided at a predetermined interval in the third direction of the first wirings. The first wiring includes a metal plug layer and a barrier metal film. A standard electrode potential of a metal that forms the barrier metal film is higher than a standard electrode potential of a metal that forms the variable resistive layer.

Abstract: According to one embodiment, a nonvolatile memory device includes a first wiring, a second wiring, and a memory cell that is disposed at a position where the first and second wirings cross so as to be interposed between the first and second wirings. The memory cell includes a variable resistive layer and a tunnel barrier layer that is formed of an insulating film provided in contact with the variable resistive layer. The tunnel barrier layer is provided close to the first wiring to which a positive voltage with applied during set operation changing the variable resistive layer to a low-resistance state from a high-resistance state.

Abstract: A method of driving a nonvolatile memory element including a variable resistance element having a state reversibly changing between low and high resistance states by an applied electrical signal and a transistor serially connected to the variable resistance element. The method including: setting the variable resistance element to the low resistance state by applying a first gate voltage to a gate of the transistor and applying a first write voltage negative with respect to a first electrode; and changing a resistance value of the transistor obtained in a low-resistance write operation, when a value of current passing through the variable resistance element in the setting of the low resistance state or a resistance value of the nonvolatile memory element in the case where the variable resistance element is in the low resistance state is outside a predetermined range.

Abstract: In a nonvolatile memory element, when a voltage value of an electric pulse has a relationship of V2>V1>0 V>V3>V4 and a resistance value of a variable resistance layer has a relationship of R3>R2>R4>R1, the resistance value of the variable resistance layer becomes: R2, when the electric pulse having a voltage value of V2 or greater is applied between electrodes; R4, when the electric pulse having a voltage value of V4 or smaller is applied between the electrodes; R3, when the resistance value of the variable resistance layer is R2 and the electric pulse having a voltage value of V3 is applied between the electrodes; and R1, when the resistance value of the variable resistance layer is R4 and the electric pulse having a voltage value of V1 is applied between the electrodes.

Abstract: In a driving method of a non-volatile memory element, the polarity of a write voltage pulse applied to change a variable resistance layer from a high-resistance state to a low-resistance state is such that an input/output terminal which is more distant from the variable resistance element becomes a source terminal, and when a first write voltage pulse is applied to change the variable resistance layer in the high-resistance state to the low-resistance state, a first gate voltage is applied to a gate terminal, while when a second write voltage pulse which is greater in absolute value of voltage than the first write voltage pulse is applied to change the variable resistance layer in an excess-resistance state to the low-resistance state, a second gate voltage which is smaller in absolute value than the first gate voltage is applied to the gate terminal.

Abstract: A nonvolatile memory device includes: a first electrode; a second electrode; and a variable resistance layer which includes: a first oxide layer including a first metal oxide; a second oxide layer located between and in contact with the first oxide layer and a second electrode including a second metal oxide and having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first oxide layer; and a local region located in the first oxide layer and the second oxide layer, having contact with the second electrode and no contact with the first electrode, and having a degree of oxygen deficiency higher than the degree of oxygen deficiency of the second oxide layer and different from the degree of oxygen deficiency of the first oxide layer.