Abstract: According to one embodiment, a plurality of first wirings are arranged along a first direction and a second direction that intersect each other and extending in a third direction perpendicular to the first and second directions. A plurality of second wirings extend in the second direction and are provided at predetermined intervals along the third direction of the first wirings. N channel field-effect transistors are provided at ends of the first wirings. Memory cells are placed at intersections of the first wirings and the second wirings. The memory cells are formed of a variable resistive layer of which the first wiring side is large in resistivity and the second wiring side is small in resistivity.

Abstract: According to one embodiment, a timing measuring circuit is provided with N (N is an integer of 2 or more) delay circuits and a comparison circuit. The N delay circuits delay a reference signal by different delay times. The comparison circuit outputs N timing adjustment values based on results of comparison between the reference signal and N output signals from the delay circuits.

Abstract: According to one embodiment, a plurality of first wirings are disposed in a first direction and a second direction which intersect with each other, and extended in a third direction. A second wiring stack is configured to include second wirings and interlayer insulating films which are extended and alternately stacked in the second direction. A memory cell includes, in the first direction, a first variable resistive layer which is disposed on a side near the first wiring and a second variable resistive layer which is disposed on a side near the second wiring. The second variable resistive layer is disposed between the interlayer insulating films in the third direction, and made of a material which is obtained by oxidizing the second wiring.

Abstract: According to one embodiment, a plurality of first wirings is disposed in first and second directions crossing each other and extends in a third direction perpendicular to the first and second directions. Second wirings extend in the second direction and are provided at a predetermined interval in the third direction of the first wirings. The first wiring includes a metal plug layer and a barrier metal film. A standard electrode potential of a metal that forms the barrier metal film is higher than a standard electrode potential of a metal that forms the variable resistive layer.

Abstract: In accordance with an embodiment, a semiconductor memory device includes a substrate, first and second wirings on the substrate across each other, and a storage element at an intersection of the first and second wirings between the first and second wirings. The storage element includes first and second electrodes having first and second materials, respectively, a first film having a first dielectric constant, and a second film having a second dielectric constant lower than the first dielectric constant. The first film is formed on the first electrode. The second electrode is formed on the first film. The second film is disposed between the second electrode and the first film. An energy difference between a vacuum level and a Fermi level of the second material is equal to or more than an energy difference between the vacuum level and a Fermi level of the first material.

Abstract: According to one embodiment, a nonvolatile memory device includes a first wiring, a second wiring, and a memory cell that is disposed at a position where the first and second wirings cross so as to be interposed between the first and second wirings. The memory cell includes a variable resistive layer and a tunnel barrier layer that is formed of an insulating film provided in contact with the variable resistive layer. The tunnel barrier layer is provided close to the first wiring to which a positive voltage with applied during set operation changing the variable resistive layer to a low-resistance state from a high-resistance state.

Abstract: An elastic composite material containing a base polymer of a simple substance or a mixture of rubber or thermoplastic elastomer as a base material, and a hard porous carbon material containing carbide of defatted bran and carbide of phenolic resin. The hard porous carbon material is added in a ratio of 200 parts or more by weight relative to 100 parts by weight of the base polymer.

Abstract: Provided is a color conversion table creation method for creating a color conversion table for an image forming apparatus which forms an image by performing, on an input color value with total use amount of color material exceeding set amount, a process for reducing the total use amount of color material, the table presenting correspondence between the input color value input to the image forming apparatus and an output color value in a device-independent color space. The method includes: acquiring an input color value of a patch image for creating the table; when the total use amount of color material defined by the acquired input color value is around the set amount, adjusting the input color value to have a smaller difference between the total use amount and the set amount; and creating the color conversion table using the patch image with the adjusted input color value.

Abstract: According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes.

Abstract: In accordance with an embodiment, a manufacturing method of a resistive element film includes sequentially repeating, a desired number of times, first and second film formation cycles. In the first film formation cycle, an insulating film is formed up to a continuous layer by an ALD film formation method under a first condition. In the second film formation cycle a metal film is formed on the insulating film up to a continuous layer by the ALD film formation method under a second condition.

Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 ? and about 100 ?, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 ? and about 100 ?, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

Abstract: A semiconductor memory device according to an embodiment includes a control circuit configured to apply a first voltage to a selected first line, apply a second voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively. The control circuit includes a detection circuit configured to detect a transition of a resistance state of a selected memory cell using a reference voltage. The control circuit is configured to execute a read operation in which the control circuit applies the third voltage to the selected first line and the non-selected first line, applies the second voltage to the selected second line, and applies the fourth voltage to the non-selected second line, and set the reference voltage based on a voltage value of the selected second line.

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.

Abstract: A method of fabricating a resistive random access memory (ReRAM) cell may include forming a set of nanolaminate structures over an electrode, such that each structure includes at least one first element oxide layer and at least one second element oxide layer. The overall set is operable as a resistive switching layer in a ReRAM cell. In this set, an average atomic ratio of the first element to the second element is different in at least two nanolaminate structures. This ratio may be less in nanolaminate structures that are closer to electrodes than in the middle nanolaminate structures. Alternatively, this ratio may increase from one end of the set to another. The first element may be less electronegative than the second elements. The first element may be hafnium, while the second element may be one of zirconium, aluminum, titanium, tantalum, or silicon.

Abstract: Provided are resistive random access memory (ReRAM) cells, each having three or more resistive states and being capable of storing multiple bits of data, as well as methods of fabricating and operating such ReRAM cells. Such ReRAM cells or, more specifically, their resistive switching layer have wide range of resistive states and are capable of being very conductive (e.g., about 1 kOhm) in one state and very resistive (e.g., about 1 MOhm) in another state. In some embodiments, a resistance ratio between resistive states may be between 10 and 1,000 even up to 10,000. The resistive switching layers also allow establishing stable and distinct intermediate resistive states that may be assigned different data values. These layers may be configured to switching between their resistive states using fewer programming pulses than conventional systems by using specific materials, switching pluses, and resistive state threshold.

Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.

Abstract: According to an embodiment, a nonvolatile memory device includes a first wiring extending to a first direction, a second wiring disposed on the first wiring in a second direction which is orthogonal to the first direction, a first insulating film provided between the first wiring and the second wiring, a bit line extending in the second direction, and a variable resistance film contacting an end portion of the first wiring, an end portion of the second wiring, and an end portion of the first insulating film. A dielectric constant of a center portion between the first and second wirings in the second direction is higher than at vicinities of the first and the second wirings. The variable resistance film is disposed between the bit line and the first wiring, between the bit line and the second wiring, and between the bit line and the first insulating film.

Abstract: An electronic device includes a planar display and a touch panel, which overlaps the display. The touch panel has a detection zone that covers at least a vertical distance which is less than a first value and greater than a second value which is smaller than the first value and where two dimensional coordinates and the vertical distance can be detected. The detection zone has a first zone that covers the vertical distance from the first value to the second value and includes a center of the touch panel with respect to the two dimensional coordinates. The first zone, in which the vertical distance is a specific value between the first value and the second value, narrows as the specific value increases from the second value toward the first value.

Abstract: Provided is a color conversion table creation method for creating a color conversion table for an image forming apparatus which forms an image by performing, on an input color value with total use amount of color material exceeding set amount, a process for reducing the total use amount of color material, the table presenting correspondence between the input color value input to the image forming apparatus and an output color value in a device-independent color space. The method includes: acquiring an input color value of a patch image for creating the table; when the total use amount of color material defined by the acquired input color value is around the set amount, adjusting the input color value to have a smaller difference between the total use amount and the set amount; and creating the color conversion table using the patch image with the adjusted input color value.