Abstract: Provided is a color conversion table creation method for creating a color conversion table for an image forming apparatus which forms an image by performing, on an input color value with total use amount of color material exceeding set amount, a process for reducing the total use amount of color material, the table presenting correspondence between the input color value input to the image forming apparatus and an output color value in a device-independent color space. The method includes: acquiring an input color value of a patch image for creating the table; when the total use amount of color material defined by the acquired input color value is around the set amount, adjusting the input color value to have a smaller difference between the total use amount and the set amount; and creating the color conversion table using the patch image with the adjusted input color value.

Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

Abstract: According to one embodiment, a resistance change element includes: a first electrode; a second electrode; and a resistance change film provided between the first electrode and the second electrode, and the resistance change film including: a first transition metal oxide-containing layer; a second transition metal oxide-containing layer; and an intermediate layer provided between the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, the intermediate layer having a higher crystallization temperature than the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, and the intermediate layer including an amorphous material.

Abstract: A control circuit controls a voltage applied to a memory cell array. A first electrode contacts to a first surface of a variable resistance element, while a second electrode contacts to a second surface of the variable resistance element. The first electrode is configured by a metal, and the second electrode is configured by a P type semiconductor. The control unit, when performing a setting operation of a memory cell, applies a voltage such that a current flows in a direction from the first electrode toward the second electrode.

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.

Abstract: Provided are resistive random access memory (ReRAM) cells, each having three or more resistive states and being capable of storing multiple bits of data, as well as methods of fabricating and operating such ReRAM cells. Such ReRAM cells or, more specifically, their resistive switching layer have wide range of resistive states and are capable of being very conductive (e.g., about 1 kOhm) in one state and very resistive (e.g., about 1 MOhm) in another state. In some embodiments, a resistance ratio between resistive states may be between 10 and 1,000 even up to 10,000. The resistive switching layers also allow establishing stable and distinct intermediate resistive states that may be assigned different data values. These layers may be configured to switching between their resistive states using fewer programming pulses than conventional systems by using specific materials, switching pluses, and resistive state threshold.

Abstract: A semiconductor memory device according to an embodiment includes a control circuit configured to apply a first voltage to a selected first line, apply a second voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively. The control circuit includes a detection circuit configured to detect a transition of a resistance state of a selected memory cell using a reference voltage. The control circuit is configured to execute a read operation in which the control circuit applies the third voltage to the selected first line and the non-selected first line, applies the second voltage to the selected second line, and applies the fourth voltage to the non-selected second line, and set the reference voltage based on a voltage value of the selected second line.

Abstract: An elastic composite material containing a base polymer of a simple substance or a mixture of rubber or thermoplastic elastomer as a base material, and a hard porous carbon material containing carbide of defatted bran and carbide of phenolic resin. The hard porous carbon material is added in a ratio of 200 parts or more by weight relative to 100 parts by weight of the base polymer.

Abstract: A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.

Abstract: In accordance with an embodiment, a resistive random access memory device includes a substrate, first and second wiring lines, and a storage cell. The first and second wiring lines are disposed on the substrate so as to intersect each other. The storage cell is disposed between the first and second wiring lines at the intersection of the first and second wiring lines and includes a first electrode, a resistive switching film on the first electrode, a second electrode on the resistive switching film, and a tantalum oxide (TaOx) layer. The first electrode is electrically connected to the first wiring line. The second electrode is electrically connected to the second wiring line. The tantalum oxide (TaOx) layer is disposed between the first electrode and the resistive switching film and is in contact with the resistive switching film.

Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 ? and about 100 ?, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

Abstract: An electronic device includes a planar display and a touch panel, which overlaps the display. The touch panel has a detection zone that covers at least a vertical distance which is less than a first value and greater than a second value which is smaller than the first value and where two dimensional coordinates and the vertical distance can be detected. The detection zone has a first zone that covers the vertical distance from the first value to the second value and includes a center of the touch panel with respect to the two dimensional coordinates. The first zone, in which the vertical distance is a specific value between the first value and the second value, narrows as the specific value increases from the second value toward the first value.

Abstract: Provided are methods of forming nonvolatile memory elements using atomic layer deposition techniques, in which at least two different layers of a memory element are deposited sequentially and without breaking vacuum in a deposition chamber. This approach may be used to prevent oxidation of various materials used for electrodes without a need for separate oxygen barrier layers. A combination of signal lines and resistive switching layers may be used to cap the electrodes and to minimize their oxidation. As such, fewer layers are needed in a memory element. Furthermore, atomic layer deposition allows more precise control of electrode thicknesses. In some embodiments, a thickness of an electrode may be less than 50 Angstroms. Overall, atomic layer deposition of electrodes and resistive switching layers lead to smaller thicknesses of entire memory elements making them more suitable for low aspect ratio features of advanced nodes.

Abstract: A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

Abstract: A method of fabricating a resistive random access memory (ReRAM) cell may include forming a set of nanolaminate structures over an electrode, such that each structure includes at least one first element oxide layer and at least one second element oxide layer. The overall set is operable as a resistive switching layer in a ReRAM cell. In this set, an average atomic ratio of the first element to the second element is different in at least two nanolaminate structures. This ratio may be less in nanolaminate structures that are closer to electrodes than in the middle nanolaminate structures. Alternatively, this ratio may increase from one end of the set to another. The first element may be less electronegative than the second elements. The first element may be hafnium, while the second element may be one of zirconium, aluminum, titanium, tantalum, or silicon.

Abstract: According to an embodiment, a first impurity diffusion layer is provided in a region lower than a drain region and the first impurity diffusion layer diffuses impurities of a second conductivity type. A second impurity diffusion layer is provided between the drain region and the first impurity diffusion layer, and the second impurity diffusion layer diffuses impurities of a first conductivity type or the second conductivity type, and a concentration of the second impurity diffusion layer is lower than that of the first conductivity type of the drain region and that of the second conductivity type of the first impurity diffusion layer.

Abstract: A memory cell array includes first wiring lines, and second wiring lines, the first and second wiring lines intersecting, and memory cells disposed in the intersections of the first and second wiring lines, the memory cells including a variable resistance element. A control circuit controls voltages of selected first and second wiring lines. The first wiring lines are arranged at a first pitch in a first direction perpendicular to a substrate and extend in a second direction parallel to the substrate. The second wiring lines are arranged at a second pitch in the second direction and extend in the first direction. The control circuit is configured to change voltages applied to a selected first wiring line according to the positions of the selected first wiring lines in the first direction.

Abstract: Disclosed is an electronic device including: a display section that displays information; an electrostatic-capacitance touch panel layer that allows visible light corresponding to display contents of the display section to pass through the touch panel layer and that determines a two-dimensional coordinate indicated by an indicator having conductivity; glass that protects the touch panel layer and that allows visible light corresponding to display contents of the display section to pass through the glass; a depression sensor that detects deformation of the glass; and a control section that validates a two-dimensional coordinate when a plurality of two-dimensional coordinates are determined by the touch panel layer and when deformation is detected by the depression sensor, the two-dimensional coordinate being determined last among the plurality of two-dimensional coordinates.

Abstract: Disclosed is an electronic device including: a display section that displays information; an electrostatic-capacitance touch panel layer that allows visible light corresponding to display contents of the display section to pass through the touch panel layer and that determines a pair of two-dimensional coordinates indicated by an indicator having conductivity; glass that protects the touch panel layer and that allows visible light corresponding to display contents of the display section to pass through the glass; a depression sensor that detects deformation of the glass; and a control section that validates a pair of two-dimensional coordinates when a plurality of pairs of two-dimensional coordinates are determined by the touch panel layer and when deformation is detected by the depression sensor, the pair of two-dimensional coordinates being determined last among the plurality of pairs of two-dimensional coordinates.