Patents by Inventor Takeshi Yamaguchi

Takeshi Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150042603
    Abstract: Disclosed is an electronic device including: a display section that displays information; an electrostatic-capacitance touch panel layer that allows visible light corresponding to display contents of the display section to pass through the touch panel layer and that determines a two-dimensional coordinate indicated by an indicator having conductivity; glass that protects the touch panel layer and that allows visible light corresponding to display contents of the display section to pass through the glass; a depression sensor that detects deformation of the glass; and a control section that validates a two-dimensional coordinate when a plurality of two-dimensional coordinates are determined by the touch panel layer and when deformation is detected by the depression sensor, the two-dimensional coordinate being determined last among the plurality of two-dimensional coordinates.
    Type: Application
    Filed: February 7, 2014
    Publication date: February 12, 2015
    Inventors: Tomoki TAKANO, Takeshi YAMAGUCHI, Yuuichi TAKIZAWA
  • Publication number: 20150042610
    Abstract: Disclosed is an electronic device including: a display section that displays information; an electrostatic-capacitance touch panel layer that allows visible light corresponding to display contents of the display section to pass through the touch panel layer and that determines a pair of two-dimensional coordinates indicated by an indicator having conductivity; glass that protects the touch panel layer and that allows visible light corresponding to display contents of the display section to pass through the glass; a depression sensor that detects deformation of the glass; and a control section that validates a pair of two-dimensional coordinates when a plurality of pairs of two-dimensional coordinates are determined by the touch panel layer and when deformation is detected by the depression sensor, the pair of two-dimensional coordinates being determined last among the plurality of pairs of two-dimensional coordinates.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 12, 2015
    Inventors: Tomoki TAKANO, Takeshi YAMAGUCHI, Yuuichi TAKIZAWA
  • Patent number: 8932506
    Abstract: The resin injection molding method of the present invention is a method for molding resins inside a cavity formed within a mold. The method comprises injecting resins into the cavity through a plurality of paths installed so as to be openable and closable and optionally maintaining the resin inside the cavity at a pressure; closing each of the plurality of paths such that the resins injected from each path converge, there being a time difference between when a first path and a second path of the plurality of paths are closed; and solidifying at least the resin which is injected from the path closed earliest with a crystallinity greater than or equal to a predetermined crystallinity degree.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: January 13, 2015
    Assignee: Mitsubishi Heavy Industries Plastic Technology
    Inventors: Naoki Toda, Satoshi Imaeda, Takeshi Yamaguchi, Toshihiko Kariya
  • Publication number: 20140375588
    Abstract: An electronic device includes a planar display and a touch panel, which overlaps the display. The touch panel has a detection zone that covers at least a vertical distance which is less than a first value and greater than a second value which is smaller than the first value and where two dimensional coordinates and the vertical distance can be detected. The detection zone has a first zone that covers the vertical distance from the first value to the second value and includes a center of the touch panel with respect to the two dimensional coordinates. The first zone, in which the vertical distance is a specific value between the first value and the second value, narrows as the specific value increases from the second value toward the first value.
    Type: Application
    Filed: September 5, 2014
    Publication date: December 25, 2014
    Inventors: Tomoki TAKANO, Takeshi YAMAGUCHI
  • Publication number: 20140374240
    Abstract: A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10? cm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.
    Type: Application
    Filed: September 8, 2014
    Publication date: December 25, 2014
    Inventors: Hieu Pham, Vidyut Gopal, Imran Hashim, Tim Minvielle, Dipankar Pramanik, Yun Wang, Takeshi Yamaguchi, Hong Sheng Yang
  • Patent number: 8916846
    Abstract: According to one embodiment, a nonvolatile memory device includes a first wiring, a second wiring, and a memory cell provided between the first wiring and the second wiring. The memory cell includes a memory layer, a rectifying element layer, and a protective resistance layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: December 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Kobayashi, Takeshi Yamaguchi, Yasuhiro Nojiri, Masaki Yamato, Hiroyuki Fukumizu
  • Patent number: 8913029
    Abstract: There is provided an electronic device that enables sufficient prevention of user's unintended manipulation during hover manipulation which enables performance of manipulation at a position distant from a touch panel. The electronic device a planar display section and a touch panel that is placed while being superimposed on the display section and that enables detection of two dimensional coordinates (x, y) of a finger, which serves as an indicator, on a surface of the display section and a vertical distance (z) from the finger. A valid zone that makes the two dimensional coordinates (x, y) valid is made narrower as the vertical distance (z) between the finger and the touch panel becomes greater. By adoption of such a configuration, it becomes possible to sufficiently prevent performance of user's unintended manipulation during hover manipulation that enables performance of manipulation at a position distant from the touch panel.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: December 16, 2014
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Tomoki Takano, Takeshi Yamaguchi
  • Publication number: 20140362017
    Abstract: An input device is equipped with a touch panel for detecting an input, a coordinates acquiring unit for detecting input coordinates which are coordinates of the input detected by the touch panel, and a pull manipulation judging unit which, when an input to an input detection surface which is a surface on which the touch panel is placed, makes effective the Z coordinate in the direction perpendicular to the input detection surface among the input coordinates detected by the coordinates acquiring unit.
    Type: Application
    Filed: December 5, 2012
    Publication date: December 11, 2014
    Applicant: PANASONIC CORPORATION
    Inventor: Takeshi Yamaguchi
  • Publication number: 20140361235
    Abstract: A nonvolatile resistive memory element has a novel variable resistance layer that includes a metal nitride, a metal oxide-nitride, a two-metal oxide-nitride, or a multilayer stack thereof. One method of forming the novel variable resistance layer comprises an interlayer deposition procedure, in which metal oxide layers are interspersed with metal nitride layers and then converted into a substantially homogeneous layer by an anneal process. Another method of forming the novel variable resistance layer comprises an intralayer deposition procedure, in which various ALD processes are sequentially interleaved to form a metal oxide-nitride layer. Alternatively, a metal oxide is deposited, nitridized, and annealed to form the variable resistance layer or a metal nitride is deposited, oxidized, and annealed to form the variable resistance layer.
    Type: Application
    Filed: August 26, 2014
    Publication date: December 11, 2014
    Inventors: Yun Wang, Tony P. Chiang, Imran Hashim, Tim Minvielle, Takeshi Yamaguchi
  • Publication number: 20140363920
    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Inventors: Zhendong Hong, Vidyut Gopal, Imran Hashim, Randall J. Higuchi, Tim Minvielle, Hieu Pham, Takeshi Yamaguchi
  • Patent number: 8906736
    Abstract: A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 ?cm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: December 9, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Hieu Pham, Vidyut Gopal, Imran Hashim, Tim Minvielle, Dipankar Pramanik, Yun Wang, Takeshi Yamaguchi, Hong Sheng Yang
  • Patent number: 8895952
    Abstract: A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Kobayashi, Kazuhiko Yamamoto, Kenji Aoyama, Shigeto Oshino, Kei Watanabe, Shinichi Nakao, Satoshi Ishikawa, Takeshi Yamaguchi
  • Patent number: 8890109
    Abstract: Provided are resistive random access memory (ReRAM) cells including resistive switching layers and thermally isolating structures for limiting heat dissipation from the switching layers during operation. Thermally isolating structures may be positioned within a stack or adjacent to the stack. For example, a stack may include one or two thermally isolating structures. A thermally isolating structure may directly interface with a switching layer or may be separated by, for example, an electrode. Thermally isolating structures may be formed from materials having a thermal conductivity of less than 1 W/m*K, such as porous silica and mesoporous titanium oxide. A thermally isolating structure positioned in series with a switching layer generally has a resistance less than the low resistance state of the switching layer. A thermally isolating structure positioned adjacent to a switching layer may have a resistance greater than the high resistance state of the switching layer.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 18, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi
  • Patent number: 8883557
    Abstract: A method of fabricating a resistive random access memory (ReRAM) cell may include forming a set of nanolaminate structures over an electrode, such that each structure includes at least one first element oxide layer and at least one second element oxide layer. The overall set is operable as a resistive switching layer in a ReRAM cell. In this set, an average atomic ratio of the first element to the second element is different in at least two nanolaminate structures. This ratio may be less in nanolaminate structures that are closer to electrodes than in the middle nanolaminate structures. Alternatively, this ratio may increase from one end of the set to another. The first element may be less electronegative than the second elements. The first element may be hafnium, while the second element may be one of zirconium, aluminum, titanium, tantalum, or silicon.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: November 11, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Chien-Lan Hsueh, Vidyut Gopal, Randall J. Higuchi, Takeshi Yamaguchi
  • Publication number: 20140326939
    Abstract: According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes.
    Type: Application
    Filed: September 11, 2013
    Publication date: November 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaki YAMATO, Takeshi Yamaguchi, Shigeki Kobayashi
  • Publication number: 20140320429
    Abstract: An electronic device includes a housing, a planar display section, a planar transparent member, a touch panel layer which detects two-dimensional coordinates of an indicator having a predetermined conductivity along a surface of the display section and a vertical distance to the indicator, and an acceleration detection section which detects at least one of an acceleration of the housing and an acceleration of the transparent member. The two-dimensional coordinates are determined as effective coordinates when the vertical distance is equal to or smaller than a first value. The two-dimensional coordinates are determined as the effective coordinates when the vertical distance is more than the first value and is equal to or smaller than a second value more than the first value, and the acceleration detection section detects a predetermined acceleration.
    Type: Application
    Filed: March 4, 2014
    Publication date: October 30, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Tomoki TAKANO, Takeshi YAMAGUCHI
  • Publication number: 20140319443
    Abstract: Provided are methods of forming nonvolatile memory elements using atomic layer deposition techniques, in which at least two different layers of a memory element are deposited sequentially and without breaking vacuum in a deposition chamber. This approach may be used to prevent oxidation of various materials used for electrodes without a need for separate oxygen barrier layers. A combination of signal lines and resistive switching layers may be used to cap the electrodes and to minimize their oxidation. As such, fewer layers are needed in a memory element. Furthermore, atomic layer deposition allows more precise control of electrode thicknesses. In some embodiments, a thickness of an electrode may be less than 50 Angstroms. Overall, atomic layer deposition of electrodes and resistive switching layers lead to smaller thicknesses of entire memory elements making them more suitable for low aspect ratio features of advanced nodes.
    Type: Application
    Filed: July 10, 2014
    Publication date: October 30, 2014
    Inventors: Yun Wang, Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi
  • Publication number: 20140316350
    Abstract: A bottomed, tubular hollow elastic body that opens toward an outlet side of a drug solution flow path is accommodated and arranged in an accommodation part formed in a housing, and a middle protrusion is provided protruding toward an inlet side of the drug solution flow path from a center part of a bottom wall of the hollow elastic body. Insertion of a male luer causes the bottom wall of the hollow elastic body to be elastically deformed so as to enter inside a peripheral wall, increasing the volume of the drug solution flow path, which is formed between an outer surface of the hollow elastic body and an inner surface of the accommodation part. Removing the male luer and canceling the elastic deformation of the hollow elastic body causes the volume of the drug solution flow path to be reduced.
    Type: Application
    Filed: December 27, 2012
    Publication date: October 23, 2014
    Applicant: NIPRO CORPORATION
    Inventors: Takeshi Yamaguchi, Tomohiro Uchimura, Kohzo Ishikura
  • Publication number: 20140315369
    Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.
    Type: Application
    Filed: June 27, 2014
    Publication date: October 23, 2014
    Inventors: Yun Wang, Tony P. Chiang, Imran Hashim, Tim Minvielle, Dipankar Pramanik, Takeshi Yamaguchi
  • Patent number: 8860002
    Abstract: Provided are ReRAM cells, each having at least one interface between an electrode and a resistive switching layers with a maximum field value of less than 0.25. The electrode materials forming such interfaces include tantalum nitrides doped with lanthanum, aluminum, erbium yttrium, or terbium (e.g., TaX(Dopant)YN, where X is at least about 0.95). The electrode materials have low work functions (e.g., less than about 4.5 eV). At the same time, the resistive switching materials have high relative dielectric permittivities (e.g., greater than about 30) and high electron affinities (greater than about for 3.5 eV). Niobium oxide is one example of a suitable resistive switching material. Another electrode interfacing the resistive switching layer may have different characteristics and, in some embodiments, may be an inert electrode.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: October 14, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Mihir Tendulkar, Imran Hashim, Tim Minvielle, Yun Wang, Takeshi Yamaguchi