Patents by Inventor Taku Ogura
Taku Ogura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8446765Abstract: A semiconductor device includes a semiconductor substrate having first and second edge lines, address pads along the first edge line, and memory mats, each including normal memory blocks and a spare memory block. Each normal memory block has nonvolatile memory cells and is a unit of batch erase. The memory mats are arranged in a U-shaped area having a hollow portion facing the second edge line. The device includes column decoders arranged correspondingly to the memory mats, an analog/logic circuit arranged in the hollow portion, and a power supply pad arranged between the analog/logic circuit and the second edge line. The analog/logic circuit includes a charge pump circuit. The device further includes a first power supply interconnection supplying power supply voltage to the charge pump circuit from the power supply pad, and a second power supply interconnection supplying power supply voltage to the column decoder from the power supply pad.Type: GrantFiled: May 25, 2012Date of Patent: May 21, 2013Assignee: Renesas Electronics CorporationInventors: Taku Ogura, Tadaaki Yamauchi, Hidenori Mitani, Takashi Kubo, Kengo Aritomi
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Publication number: 20130115359Abstract: Provided is a dried noodle having a porosity in the cross-sectional area of the noodle of from 0.1 to 15%, a unit porosity in the cross-sectional area of the noodle of from 0.01 to 1%, a gelatinization degree of 30 to 75% and a porous structure.Type: ApplicationFiled: December 27, 2012Publication date: May 9, 2013Applicant: TOYO SUISAN KAISHA, LTD.Inventors: Junya KANAYAMA, Hisashi SUGIYAMA, Masafumi YAMAKOSHI, Taku OGURA
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Patent number: 8339862Abstract: According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one correspoType: GrantFiled: December 24, 2008Date of Patent: December 25, 2012Assignee: Genusion, Inc.Inventors: Natsuo Aiika, Shoii Shukuri, Satoshi Shimizu, Taku Ogura
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Patent number: 8337710Abstract: The present invention relates to an ozone oxidation accelerator containing a compound of which a 0.5% by mass aqueous solution at 25° C. has a dynamic surface tension at 100 msec of 70 mN/m or less and a dynamic surface tension at 30 sec of 55 to 67 mN/m, and an ozone oxidation accelerator composition containing the ozone oxidation accelerator. The present invention also relates to an ozone treatment method including a step of supplying ozone into water to be treated that contains a substance to be treated, in the presence of the ozone oxidation accelerator composition.Type: GrantFiled: May 23, 2011Date of Patent: December 25, 2012Assignee: LION CorporationInventors: Yoshikuni Takeuchi, Taku Ogura, Masaru Tamura
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Publication number: 20120230107Abstract: A semiconductor device includes a semiconductor substrate having first and second edge lines, address pads along the first edge line, and memory mats, each including normal memory blocks and a spare memory block. Each normal memory block has nonvolatile memory cells and is a unit of batch erase. The memory mats are arranged in a U-shaped area having a hollow portion facing the second edge line. The device includes column decoders arranged correspondingly to the memory mats, an analog/logic circuit arranged in the hollow portion, and a power supply pad arranged between the analog/logic circuit and the second edge line. The analog/logic circuit includes a charge pump circuit. The device further includes a first power supply interconnection supplying power supply voltage to the charge pump circuit from the power supply pad, and a second power supply interconnection supplying power supply voltage to the column decoder from the power supply pad.Type: ApplicationFiled: May 25, 2012Publication date: September 13, 2012Applicant: Renesas Electronics CorporationInventors: Taku Ogura, Tadaaki Yamauchi, Hidenori Mitani, Takashi Kubo, Kengo Aritomi
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Patent number: 8208303Abstract: A memory apparatus includes a control circuit, a plurality of memory arrays, each of which contains a plurality of memory cells, and a current detecting circuit. The current detecting circuit measures a quantity of a current of a first memory array. A redundancy information is changed when the quantity of the current of the first memory array is over a first current quantity detected by the current detecting circuit. The control circuit controls an access to the memory arrays, and changes the access to the first memory array to a second memory array in accordance with the redundancy information.Type: GrantFiled: July 7, 2011Date of Patent: June 26, 2012Assignee: Renesas Electronics CorporationInventors: Taku Ogura, Tadaaki Yamauchi, Hidenori Mitani, Takashi Kubo, Kengo Aritomi
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Publication number: 20120112265Abstract: A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.Type: ApplicationFiled: January 13, 2012Publication date: May 10, 2012Applicant: GENUSION, INC.Inventors: Natsuo AJIKA, Shoji Shukuri, Satoshi Shimizu, Taku Ogura
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Publication number: 20120080053Abstract: Disclosed is a cleaning method which can remove, particularly, all of an organic contaminant, a particle contaminant, and a metal contaminant adhered to a semiconductor substrate at a high cleaning level, and which can realize the reduction in environmental load caused by the cleaning. The method of cleaning the semiconductor substrate includes a first cleaning process of cleaning the semiconductor substrate with a cleaning composition including a transition-metal-containing water-soluble salt (A), a chelating agent (B1), and a peroxide (C), a ratio of the chelating agent (B1) to the transition-metal-containing water-soluble salt (A) being 0.5 molar equivalent or more; and a second cleaning process of cleaning the semiconductor substrate, which is cleaned through the first cleaning process, with an acidic solution containing a chelating agent (B2).Type: ApplicationFiled: April 30, 2010Publication date: April 5, 2012Applicant: LION CORPORATIONInventors: Makoto Hidaka, Taku Ogura, Maiko Kikuchi, Motohiro Kageyama, Masayuki Takashima
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Patent number: 8106443Abstract: A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.Type: GrantFiled: October 6, 2008Date of Patent: January 31, 2012Assignee: Genusion, Inc.Inventors: Natsuo Ajika, Shoji Shukuri, Satoshi Shimizu, Taku Ogura
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Patent number: 8107300Abstract: According to an one aspect of the present invention, it is provided a non-volatile semiconductor memory device comprising: a first N type well; a plurality of P type non-volatile memory cells arranged in matrix and formed in the N type well; a plurality of sub-bit lines, each of the sub-bit lines being connected to drains of the P type non-volatile memory cells in a respective one of columns of the matrix; a first P type well; and a plurality of N type selection transistors, each of the selection transistors selectively connecting a respective one of sub-bit lines to a corresponding one of main bit lines.Type: GrantFiled: February 4, 2008Date of Patent: January 31, 2012Assignee: Genusion, Inc.Inventors: Taku Ogura, Natsuo Ajika
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Publication number: 20110261617Abstract: A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.Type: ApplicationFiled: July 7, 2011Publication date: October 27, 2011Applicant: Renesas Electronics CorporationInventors: Taku OGURA, Tadaaki Yamauchi, Hidenori Mitani, Takashi Kubo, Kengo Aritomi
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Publication number: 20110223073Abstract: The present invention relates to an ozone oxidation accelerator containing a compound of which a 0.5% by mass aqueous solution at 25° C. has a dynamic surface tension at 100 msec of 70 mN/m or less and a dynamic surface tension at 30 sec of 55 to 67 mN/m, and an ozone oxidation accelerator composition containing the ozone oxidation accelerator. The present invention also relates to an ozone treatment method including a step of supplying ozone into water to be treated that contains a substance to be treated, in the presence of the ozone oxidation accelerator composition.Type: ApplicationFiled: May 23, 2011Publication date: September 15, 2011Applicant: LION CORPORATIONInventors: YOSHIKUNI TAKEUCHI, TAKU OGURA, MASARU TAMURA
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Patent number: 8000137Abstract: A nonvolatile semiconductor memory device includes a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.Type: GrantFiled: March 9, 2009Date of Patent: August 16, 2011Assignee: Genusion, Inc.Inventors: Taku Ogura, Natsuo Ajika, Shoji Shukuri, Satoshi Shimizu, Yoshiki Kawajiri, Masaaki Mihara
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Patent number: 8000159Abstract: A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.Type: GrantFiled: August 3, 2010Date of Patent: August 16, 2011Assignee: Renesas Electronics CorporationInventors: Taku Ogura, Tadaaki Yamauchi, Hidenori Mitani, Takashi Kubo, Kengo Aritomi
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Patent number: 8000143Abstract: A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.Type: GrantFiled: September 23, 2010Date of Patent: August 16, 2011Assignee: Renesas Electronics CorporationInventors: Taku Ogura, Tadaaki Yamauchi, Takashi Kubo
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Patent number: 7969780Abstract: An object of this invention is to provide a rewritable nonvolatile memory cell that can have a wide reading margin, and can control both a word line and a bit line by changing the level of Vcc. As a solution, a flip-flop is formed by cross (loop) connect of inverters including memory transistors that can control a threshold voltage by charge injection into the side spacer of the transistors. In the case of writing data to one memory transistor, a high voltage is supplied to a source of the memory transistor through a source line and a high voltage is supplied to a gate of the memory transistor through a load transistor of the other side inverter. In the case of erasing the written data, a high voltage is supplied to the source of the memory transistor through the source line.Type: GrantFiled: July 11, 2007Date of Patent: June 28, 2011Assignee: Genusion, Inc.Inventors: Taku Ogura, Masaaki Mihara, Yoshiki Kawajiri
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Patent number: 7885132Abstract: An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.Type: GrantFiled: May 7, 2009Date of Patent: February 8, 2011Assignee: Renesas Electronics CorporationInventors: Takashi Kubo, Takashi Itoh, Yasuhiro Kashiwazaki, Taku Ogura, Kiyohiro Furutani
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Publication number: 20110013453Abstract: A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.Type: ApplicationFiled: September 23, 2010Publication date: January 20, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Taku OGURA, Tadaaki Yamauchi, Takashi Kubo
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Publication number: 20110002170Abstract: A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.Type: ApplicationFiled: August 3, 2010Publication date: January 6, 2011Applicant: RENESAS TECHNOLOGY CORP.Inventors: Taku OGURA, Tadaaki Yamauchi, Hidenori Mitani, Takashi Kubo, Kengo Aritomi
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Publication number: 20100319735Abstract: A cleaning composition which is capable of removing both organic soiling and particulate soiling adhered to a substrate for an electronic device with a high degree of cleanliness, and which also has minimal impact on the environment, as well as a method of cleaning a substrate for an electronic device. The present invention relates to a cleaning composition used for cleaning a substrate for an electronic device including a water-soluble salt (A) containing a transition metal, a chelating agent (B) and a peroxide (C), wherein the amount of the chelating agent (B) is not less than 0.5 molar equivalents relative to the amount of the water-soluble salt (A) containing a transition metal.Type: ApplicationFiled: February 13, 2009Publication date: December 23, 2010Applicant: Lion CorporationInventors: Makoto Hidaka, Taku Ogura