Abstract: The PROM area is adjacent to the normal memory cell area. The data writing (normal writing) and the data reading (normal reading) for normal memory cell areas and the data writing (redundant writing) for the PROM area are carried out from the side of the normal memory cell areas. The data reading (redundant reading) for the PROM area is carried out from the side of the PROM area. In the PROM area, the PROM cells having the same structure as that of the normal memory cells are connected to the redundant sub bit lines. In the redundant writing, in the select gate area, the redundant sub bit lines and main bit lines are connected. In the redundant reading, in the redundant gate area having the same layout as that of the select gate area, the redundant sub bit lines are connected to redundant bit lines.

Abstract: Until the number of pulse application n reaches 12, as a first-half pulse, a pulse is set to have a width fixed to 2 ms, and its voltage is increased every time. As a latter-half pulse, the pulse is set to have a width fixed to 3 ms and the pulse voltage is increased every time until the maximum voltage is attained. After the maximum voltage is attained, first, the pulse of a width of 3 ms is applied twice, the pulse of a width of 4 ms with the maximum voltage is applied twice, and the pulse of a width of 5 ms with the maximum voltage is applied twice. Even after the maximum voltage is attained, change over time of a threshold voltage can be more linear. Thus, a non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in a short period of time can be provided.

Abstract: A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.

Abstract: A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.

Abstract: A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits; respectively, and stored in a memory cell array.

Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

Abstract: Particular blocks are a boot block and parameter block having a storage capacity smaller than that of a general block. In the case where a boot block is not required, a signal BOOTE is set at an L level. In the case where a signal BLKSEL is at an H level in an erasure mode, a control unit selects four blocks aligned in a horizontal direction at the same time. The control unit also selects two blocks simultaneously in the vertical direction. As a result, the particular eight blocks are selected. The boot block and parameter block can be erased collectively as one block having a capacity similar to that of a general block. Therefore, a flash memory corresponding to the case of including a boot block and not including a boot block can be implemented simultaneously with one chip. Thus, the designing and fabrication process can be simplified.

Abstract: In a charge pump unit circuit, a P channel MOS transistor is connected between a gate and a drain of switching N channel MOS transistor. The P channel MOS transistor is controlled to be on/off by a switching circuit. A voltage doubling circuit generates a clock signal having amplitude twice that of power supply voltage. The clock signal is applied to a capacitor to increase the potential of the gate of the N channel MOS transistor. Thus, resistance of the N channel MOS transistor sufficiently is reduced and transfer efficiency of positive charge is enhanced.

Abstract: Output nodes (Noutn, Noutp) outputting a negative potential (VN) and a positive potential (VPS) respectively are supplied with fixed potentials by reset circuits respectively when unused. Switches (SW2, SW3) conduct when generating the negative potential, while switches (SW1, SW4) conduct when generating the positive potential. Reference potentials for the generated potentials are supplied to internal nodes N10, N20) through the switches (SW1, SW3) respectively. Poly-diode elements are employed for a voltage generation part, whereby a charge pump circuit capable of generating positive and negative voltages can be implemented without remarkably changing a fabrication method.

Abstract: An object is to provide a word line boosting circuit which, regardless of varying value of the power-supply voltage, can generate a boosted voltage within a range between upper and lower limit values of threshold voltage distribution of semiconductor non-volatile memory elements. A drain boosting circuit (VCa) has a plurality of series-connected boosting stages and the number of parallel-connected capacitors is varied in each stage depending on the value of the power-supply voltage (Vcc). Comparators (OP1) to (OP3) detect resistor-divided voltage values to detect the power-supply voltage (Vcc). A decoder (DCa) generates operation signals (S1a) to (S3a) in accordance with the combination of outputs of the comparators (OP1) to (OP3), thus determining which capacitors should be connected in parallel.

Abstract: In a charge pump unit circuit, a P channel MOS transistor is connected between a gate and a drain of switching N channel MOS transistor. The P channel MOS transistor is controlled to be on/off by a switching circuit. A voltage doubling circuit generates a clock signal having amplitude twice that of power supply voltage. The clock signal is applied to a capacitor to increase the potential of the gate of the N channel MOS transistor. Thus, resistance of the N channel MOS transistor sufficiently is reduced and transfer efficiency of positive charge is enhanced.

Abstract: A flash memory having a sense amplifier is provided with a constant-current source having the positive temperature characteristic and a constant-current source having the negative temperature characteristic. The sense amplifier combines a current having the positive temperature characteristic and a current having the negative temperature characteristic to generate a verifying sense amplifier load current having no temperature characteristic, and combines a current having the positive temperature characteristic and a current having a power-supply voltage dependency to generate a normal-read sense amplifier load current. Thus, the sense amplifier has a sufficient read margin and is capable of performing an accurate verify operation.

Abstract: A flash memory having a sense amplifier is provided with a constant-current source having the positive temperature characteristic and a constant-current source having the negative temperature characteristic. The sense amplifier combines a current having the positive temperature characteristic and a current having the negative temperature characteristic to generate a verifying sense amplifier load current having no temperature characteristic, and combines a current having the positive temperature characteristic and a current having a power-supply voltage dependency to generate a normal-read sense amplifier load current. Thus, the sense amplifier has a sufficient read margin and is capable of performing an accurate verify operation.

Abstract: A voltage generation circuit includes a boost circuit boosting a power supply voltage and transmitting the boosted voltage to an output transistor according to a boost control signal, a gate boost circuit boosting a gate voltage VHbst of the output transistor according to the boost control signal, a clamp circuit having a function of clamping VHbst to a prescribed voltage, and an output transistor receiving VHbst at its gate and provided to connect the boost circuit and a voltage supply node. The clamp circuit is activated according to the boost control signal.

Abstract: A positive voltage generation circuit used in data erasure and programming with respect to a memory cell includes a positive voltage charge pump circuit generating a voltage higher than the power supply voltage, and a decouple capacitor. When the positive voltage charge pump is rendered inactive, the decouple capacitor is disconnected from an output node by a P channel MOS transistor prior to the fall of the potential at the output node. The decouple capacitor is connected to the output node again when the positive voltage charge pump is rendered active. Since the potential of the output node does not have to be boosted from the beginning by virtue of charge redistribution, power consumption can be reduced correspondingly.

Abstract: Output nodes (Noutn, Noutp) outputting a negative potential (VN) and a positive potential (VPS) respectively are supplied with fixed potentials by reset circuits respectively when unused. Switches (SW2, SW3) conduct when generating the negative potential, while switches (SW1, SW4) conduct when generating the positive potential. Reference potentials for the generated potentials are supplied to internal nodes (N10, N20) through the switches (SW1, SW3) respectively. Poly-diode elements are employed for a voltage generation part, whereby a charge pump circuit capable of generating positive and negative voltages can be implemented without remarkably changing a fabrication method.

Abstract: A reset power down mode designating signal and first and second write protect signals are provided to a control circuit. According to the states of these external control signals, the status of unconditional inhibition, unconditional permission, and lock bit (LB) dependency for the protect status of data rewrite is set for each memory block group of a memory array. Therefore, the write protect status can be set in a flexible manner for a nonvolatile semiconductor memory device.

Abstract: Every time a program pulse is applied, transition in source potential connected to a selected cell is detected and the source potential is clamped. When the source potential exists an overbit generation detection level, transition in threshold voltage of a non-selected cell connected to the same sub bit as the selected cell and existing in a different page than the selected cell is detected, and the threshold voltage is recovered. Threshold voltage verifying operation is performed on the same page as the selected cell.