Patents by Inventor Taku Ogura
Taku Ogura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100283099Abstract: A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.Type: ApplicationFiled: May 18, 2010Publication date: November 11, 2010Applicant: GENUSION, INC.Inventors: Natsuo Ajika, Shoji Shukuri, Satoshi Shimizu, Taku Ogura
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Patent number: 7821829Abstract: A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.Type: GrantFiled: June 12, 2009Date of Patent: October 26, 2010Assignee: Renesas Technology Corp.Inventors: Taku Ogura, Tadaaki Yamauchi, Takashi Kubo
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Patent number: 7782672Abstract: A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.Type: GrantFiled: October 15, 2008Date of Patent: August 24, 2010Assignee: Renesas Technology Corp.Inventors: Taku Ogura, Tadaaki Yamauchi, Hidenori Mitani, Takashi Kubo, Kengo Aritomi
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Publication number: 20100147777Abstract: The present invention relates to an ozone oxidation accelerator containing a compound of which a 0.5% by mass aqueous solution at 25° C. has a dynamic surface tension at 100 msec of 70 mN/m or less and a dynamic surface tension at 30 sec of 55 to 67 mN/m, and an ozone oxidation accelerator composition containing the ozone oxidation accelerator. The present invention also relates to an ozone treatment method including a step of supplying ozone into water to be treated that contains a substance to be treated, in the presence of the ozone oxidation accelerator composition.Type: ApplicationFiled: October 5, 2006Publication date: June 17, 2010Applicant: LION CORPORATIONInventors: Yoshikuni Takeuchi, Taku Ogura, Masaru Tamura
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Publication number: 20090251965Abstract: A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.Type: ApplicationFiled: June 12, 2009Publication date: October 8, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Taku OGURA, Tadaaki YAMAUCHI, Takashi KUBO
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Publication number: 20090244972Abstract: A nonvolatile semiconductor memory device comprises a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.Type: ApplicationFiled: March 9, 2009Publication date: October 1, 2009Applicant: GENUSION, INC.Inventors: Taku Ogura, Natsuo Ajika, Shoji Shukuri, Satoshi Shimizu, Yoshiki Kawajiri, Masaaki Mihara
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Publication number: 20090213667Abstract: An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.Type: ApplicationFiled: May 7, 2009Publication date: August 27, 2009Applicant: Renesas Technology CorporationInventors: Takashi KUBO, Takashi ITOH, Yasuhiro KASHIWAZAKI, Taku OGURA, Kiyohiro FURUTANI
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Publication number: 20090161439Abstract: According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one correspoType: ApplicationFiled: December 24, 2008Publication date: June 25, 2009Applicant: Genusion, Inc.Inventors: Natsuo Aiika, Shoii Shukuri, Satoshi Shimizu, Taku Ogura
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Patent number: 7542363Abstract: An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.Type: GrantFiled: March 18, 2005Date of Patent: June 2, 2009Assignee: Renesas Technology Corp.Inventors: Takashi Kubo, Takashi Itoh, Yasuhiro Kashiwazaki, Taku Ogura, Kiyohiro Furutani
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Publication number: 20090090961Abstract: A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.Type: ApplicationFiled: October 6, 2008Publication date: April 9, 2009Applicant: GENUSION, INC.Inventors: Natsuo Ajika, Shoji Shukuri, Satoshi Shimizu, Taku Ogura
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Publication number: 20090080252Abstract: A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array.Type: ApplicationFiled: December 2, 2008Publication date: March 26, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hidenori MITANI, Tadaaki YAMAUCHI, Taku OGURA
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Publication number: 20090073740Abstract: An object of this invention is to provide a rewritable nonvolatile memory cell that can have a wide reading margin, and can control both a word line and a bit line by changing the level of Vcc. As a solution, a flip-flop is formed by cross (loop) connect of inverters comprising memory transistors that can control a threshold voltage by charge injection into the side spacer of the transistors. In the case of writing data to one memory transistor, a high voltage is supplied to a source of the memory transistor through a source line and a high voltage is supplied to a gate of the memory transistor through a load transistor of the other side inverter. In the case of erasing the written data, a high voltage is supplied to the source of the memory transistor through the source line.Type: ApplicationFiled: July 11, 2007Publication date: March 19, 2009Applicant: GENUSION, INC.Inventors: TAKU OGURA, MASAAKI MIHARA, YOSHIKI KAWAJIRI
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Publication number: 20090052249Abstract: A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.Type: ApplicationFiled: October 15, 2008Publication date: February 26, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Taku Ogura, Tadaaki Yamauchi, Hidenori Mitani, Takashi Kubo, Kengo Aritomi
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Publication number: 20090021981Abstract: A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.Type: ApplicationFiled: September 16, 2008Publication date: January 22, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Taku OGURA, Tadaaki Yamauchi, Takashi Kubo
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Patent number: 7466592Abstract: A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array.Type: GrantFiled: August 20, 2007Date of Patent: December 16, 2008Assignee: Renesas Technology Corp.Inventors: Hidenori Mitani, Tadaaki Yamauchi, Taku Ogura
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Patent number: 7447087Abstract: A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.Type: GrantFiled: June 26, 2007Date of Patent: November 4, 2008Assignee: Renesas Technology Corp.Inventors: Taku Ogura, Tadaaki Yamauchi, Hidenori Mitani, Takashi Kubo, Kengo Aritomi
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Patent number: 7436712Abstract: A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.Type: GrantFiled: November 8, 2007Date of Patent: October 14, 2008Assignee: Renesas Technology Corp.Inventors: Taku Ogura, Tadaaki Yamauchi, Takashi Kubo
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Publication number: 20080186766Abstract: According to an one aspect of the present invention, it is provided a non-volatile semiconductor memory device comprising: a first N type well; a plurality of P type non-volatile memory cells arranged in matrix and formed in the N type well; a plurality of sub-bit lines, each of the sub-bit lines being connected to drains of the P type non-volatile memory cells in a respective one of columns of the matrix; a first P type well; and a plurality of N type selection transistors, each of the selection transistors selectively connecting a respective one of sub-bit lines to a corresponding one of main bit lines.Type: ApplicationFiled: February 4, 2008Publication date: August 7, 2008Applicant: GENUSION, INC.Inventors: Taku Ogura, Natsuo Ajika
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Publication number: 20080151625Abstract: Until the number of pulse application n reaches 12, as a first-half pulse, a pulse is set to have a width fixed to 2 ms, and its voltage is increased every time. As a latter-half pulse, the pulse is set to have a width fixed to 3 ms and the pulse voltage is increased every time until the maximum voltage is attained. After the maximum voltage is attained, first, the pulse of a width of 3 ms is applied twice, the pulse of a width of 4 ms with the maximum voltage is applied twice, and the pulse of a width of 5 ms with the maximum voltage is applied twice. Even after the maximum voltage is attained, change over time of a threshold voltage can be more linear. Thus, a non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in a short period of time can be provided.Type: ApplicationFiled: January 28, 2008Publication date: June 26, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hidenori Mitani, Fumihiko Nitta, Tadaaki Yamauchi, Taku Ogura
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Patent number: 7365578Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: GrantFiled: July 3, 2007Date of Patent: April 29, 2008Assignee: Renesas Technology Corp.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi