Patents by Inventor Takuya Futase
Takuya Futase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8222133Abstract: An object of the invention is to avoid an inconvenience at a connection portion formed by filling a metal film in a connecting hole, which has been opened in an insulating film, via a barrier metal film having a titanium nitride film stacked over a titanium film. A manufacturing method of a semiconductor device has the steps of: forming a thermal reaction Ti film over the bottom of a connecting hole by a thermal reaction using a TiCl4 gas; forming a plasma reaction Ti film by a plasma reaction using a TiCl4 gas; forming a nitrogen-rich TiN film over the surface of the plasma reaction Ti film by plasma treatment with H2 and plasma treatment with NH3 gases; repeatedly carrying out film formation by CVD using a WF6 gas and reduction using an SiH4 or B2H6 gas to form a tungsten nucleation film of a multilayer structure over the nitrogen-rich TiN film; and forming a blanket•tungsten film at 400° C. or less by CVD using WF6 and H2 gases.Type: GrantFiled: October 17, 2007Date of Patent: July 17, 2012Assignee: Renesas Electronics CorporationInventors: Takuya Futase, Takeshi Hayashi
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Publication number: 20120077321Abstract: Reliability of a semiconductor element and its product yield are improved by reducing variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. After removing unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of each thermal treatment is set to 10° C./s or more.Type: ApplicationFiled: September 23, 2011Publication date: March 29, 2012Inventors: SHIGENARI OKADA, TAKUYA FUTASE, YUTAKA INABA
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Patent number: 8110457Abstract: To provide a semiconductor device with improved reliability which includes a metal silicide layer formed by a salicide process. After forming gate electrodes, an n+-type semiconductor region, and a p+-type semiconductor region for a source or drain, a Ni1?xPtx alloy film is formed over a semiconductor substrate. The alloy film reacts with the gate electrodes, the n+-type semiconductor region, and the p+-type semiconductor region by a first heat treatment to form a metal silicide layer in a (Ni1?yPty)2Si phase. At this time, the first heat treatment is performed at a heat treatment temperature where a diffusion coefficient of Ni is larger than that of Pt. Further, the first heat treatment is performed such that a reacted part of the alloy film remains at the metal silicide layer. This results in y>x. Then, after removing the unreacted part of the alloy film, the metal silicide layer is further subjected to a second heat treatment to form a metal silicide layer in a Ni1?yPtySi phase.Type: GrantFiled: September 20, 2009Date of Patent: February 7, 2012Assignee: Renesas Electronics CorporationInventor: Takuya Futase
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Publication number: 20120009800Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).Type: ApplicationFiled: September 22, 2011Publication date: January 12, 2012Inventors: Takuya FUTASE, Tomonori Saeki, Mieko Kashi
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Patent number: 8039378Abstract: To provide a technique capable of improving the reliability of a semiconductor element and its product yield by reducing the variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate 1, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. Subsequently, after removing the unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of the first thermal treatment is set to 10° C./s or more (for example, 30 to 250° C.Type: GrantFiled: January 23, 2009Date of Patent: October 18, 2011Assignee: Renesas Electronics CorporationInventors: Shigenari Okada, Takuya Futase, Yutaka Inaba
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Publication number: 20110248355Abstract: An improvement is achieved in the performance of a semiconductor device in which a metal silicide layer is formed by a salicide process. In a main surface of a semiconductor substrate, a plurality of MISFETs are formed, each having a gate electrode, and source/drain regions over each of which the metal silicide layer is formed. The metal silicide layer is formed of a silicide of nickel and a first metal element including at least one selected from the group consisting of Pt, Pd, V, Er, and Yb. A grain size in the metal silicide layer is smaller than the width in a gate length direction of the source/drain region included in the source/drain regions of the plurality of MISFETs formed in the main surface of the semiconductor substrate, and disposed between the gate electrodes adjacent in closest proximity to each other in the gate length direction.Type: ApplicationFiled: April 13, 2011Publication date: October 13, 2011Inventor: Takuya FUTASE
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Patent number: 8034717Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).Type: GrantFiled: September 10, 2008Date of Patent: October 11, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Co., Ltd.Inventors: Takuya Futase, Tomonori Saeki, Mieko Kashi
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Publication number: 20110237061Abstract: The present invention improves the performance of a semiconductor device wherein a metal silicide layer is formed through a salicide process. A metal silicide layer is formed over the surfaces of first and second gate electrodes, n+-type semiconductor regions, and p+-type semiconductor regions through a salicide process of a partial reaction type without the use of a salicide process of a whole reaction type. In a heat treatment for forming the metal silicide layer, by heat-treating a semiconductor wafer not with an annealing apparatus using lamps or lasers but with a thermal conductive annealing apparatus using carbon heaters, a thin metal silicide layer is formed with a small thermal budget and a high degree of accuracy and microcrystals of NiSi are formed in the metal silicide layer through a first heat treatment.Type: ApplicationFiled: March 13, 2011Publication date: September 29, 2011Inventors: Tadashi Yamaguchi, Takuya Futase
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Patent number: 8021979Abstract: To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chamber for dry cleaning treatment of a deposition system, dry cleaning treatment is performed to a principal surface of the semiconductor wafer by supplying reducing gas, sequentially, heat treatment is performed to the semiconductor wafer at a first temperature of 100 to 150° C. by a showerhead which is maintained at 180° C. Next, after the semiconductor wafer is vacuum transferred from the chamber to a chamber for heat treatment, heat treatment is performed to the semiconductor wafer at a second temperature of 150 to 400° C. in the chamber, thereby removing a product remaining over the principal surface of the semiconductor wafer.Type: GrantFiled: November 29, 2010Date of Patent: September 20, 2011Assignee: Renesas Electronics CorporationInventors: Takuya Futase, Hiroshi Tobimatsu
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Patent number: 7994049Abstract: The present invention is to possible to avoid an inconvenience at a coupling portion between a barrier metal film obtained by depositing a titanium nitride film on a titanium film and thus having a film stack structure and a metal film filled, via the barrier metal film, in a connecting hole opened in an insulating film.Type: GrantFiled: June 4, 2008Date of Patent: August 9, 2011Assignee: Renesas Electronics CorporationInventor: Takuya Futase
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Publication number: 20110165743Abstract: When a natural oxide film is left at the interface between a metal silicide layer and a silicon nitride film, in various heating steps (steps involving heating of a semiconductor substrate, such as various insulation film and conductive film deposition steps) after deposition of the silicon nitride film, the metal silicide layer partially abnormally grows due to oxygen of the natural oxide film occurring on the metal silicide layer surface. A substantially non-bias (including low bias) plasma treatment is performed in a gas atmosphere containing an inert gas as a main component on the top surface of a metal silicide film of nickel silicide or the like over source/drain of a field-effect transistor forming an integrated circuit. Then, a silicon nitride film serving as an etching stop film of a contact process is deposited. As a result, without causing undesirable cutting of the metal silicide film, the natural oxide film over the top surface of the metal silicide film can be removed.Type: ApplicationFiled: March 16, 2011Publication date: July 7, 2011Inventors: TAKUYA FUTASE, Shuhei Murata, Takeshi Hayashi
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Patent number: 7964500Abstract: To solve a problem that it becomes difficult to lower contact resistance between nickel-based metal silicide and metal for contact as the result of the miniaturization of the hole. One invention of the present application is a method of manufacturing a semiconductor integrated circuit device having a MISFET subjected to silicidation of a source/drain region and the like by nickel-based metal silicide, the method performing a heat treatment for the upper surface of a silicide film in a non-plasma reducing vapor phase atmosphere containing a gas having a nitrogen-hydrogen bond as one of main gas components, before forming a barrier metal at a contact hole provided at a pre-metal insulating film.Type: GrantFiled: February 27, 2010Date of Patent: June 21, 2011Assignee: Renesas Electronics CorporationInventor: Takuya Futase
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Patent number: 7964509Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).Type: GrantFiled: January 22, 2008Date of Patent: June 21, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Takuya Futase, Tomonori Saeki, Mieko Kashi
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Patent number: 7955925Abstract: After gate insulating films, gate electrodes, and n+ type semiconductor regions and p+ type semiconductor regions for source/drain are formed, a metal film and a barrier film are formed on a semiconductor substrate. And a first heat treatment is performed so as to make the metal film react with the gate electrodes, the n+ type semiconductor region, and the p+ type semiconductor region, thereby forming a metal silicide layer formed of a monosilicide of a metal element forming the metal film. After that, the barrier film and the unreacted metal film are removed, and then a second heat treatment is performed to stabilize the metal silicide layer. The heat treatment temperature is made lower than a temperature at which a lattice size of a disilicide of the metal element and that of the semiconductor substrate become same.Type: GrantFiled: July 3, 2008Date of Patent: June 7, 2011Assignee: Renesas Electronics CorporationInventors: Shigenari Okada, Takuya Futase
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Patent number: 7923319Abstract: When a natural oxide film is left at the interface between a metal silicide layer and a silicon nitride film, in various heating steps (steps involving heating of a semiconductor substrate, such as various insulation film and conductive film deposition steps) after deposition of the silicon nitride film, the metal silicide layer partially abnormally grows due to oxygen of the natural oxide film occurring on the metal silicide layer surface. A substantially non-bias (including low bias) plasma treatment is performed in a gas atmosphere containing an inert gas as a main component on the top surface of a metal silicide film of nickel silicide or the like over source/drain of a field-effect transistor forming an integrated circuit. Then, a silicon nitride film serving as an etching stop film of a contact process is deposited. As a result, without causing undesirable cutting of the metal silicide film, the natural oxide film over the top surface of the metal silicide film can be removed.Type: GrantFiled: November 20, 2009Date of Patent: April 12, 2011Assignee: Renesas Electronics CorporationInventors: Takuya Futase, Shuhei Murata, Takeshi Hayashi
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Publication number: 20110070731Abstract: To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chamber for dry cleaning treatment of a deposition system, dry cleaning treatment is performed to a principal surface of the semiconductor wafer by supplying reducing gas, sequentially, heat treatment is performed to the semiconductor wafer at a first temperature of 100 to 150° C. by a showerhead which is maintained at 180° C. Next, after the semiconductor wafer is vacuum transferred from the chamber to a chamber for heat treatment, heat treatment is performed to the semiconductor wafer at a second temperature of 150 to 400° C. in the chamber, thereby removing a product remaining over the principal surface of the semiconductor wafer.Type: ApplicationFiled: November 29, 2010Publication date: March 24, 2011Inventors: Takuya FUTASE, Hiroshi Tobimatsu
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Patent number: 7851355Abstract: To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chamber for dry cleaning treatment of a deposition system, dry cleaning treatment is performed to a principal surface of the semiconductor wafer by supplying reducing gas, sequentially, heat treatment is performed to the semiconductor wafer at a first temperature of 100 to 150° C. by a showerhead which is maintained at 180° C. Next, after the semiconductor wafer is vacuum transferred from the chamber to a chamber for heat treatment, heat treatment is performed to the semiconductor wafer at a second temperature of 150 to 400° C. in the chamber, thereby removing a product remaining over the principal surface of the semiconductor wafer.Type: GrantFiled: May 16, 2007Date of Patent: December 14, 2010Assignee: Renesas Electronics CorporationInventors: Takuya Futase, Hiroshi Tobimatsu
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Publication number: 20100227472Abstract: To solve a problem that it becomes difficult to lower contact resistance between nickel-based metal silicide and metal for contact as the result of the miniaturization of the hole. One invention of the present application is a method of manufacturing a semiconductor integrated circuit device having a MISFET subjected to silicidation of a source/drain region and the like by nickel-based metal silicide, the method performing a heat treatment for the upper surface of a silicide film in a non-plasma reducing vapor phase atmosphere containing a gas having a nitrogen-hydrogen bond as one of main gas components, before forming a barrier metal at a contact hole provided at a pre-metal insulating film.Type: ApplicationFiled: February 27, 2010Publication date: September 9, 2010Inventor: Takuya FUTASE
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Publication number: 20100129974Abstract: When a natural oxide film is left at the interface between a metal silicide layer and a silicon nitride film, in various heating steps (steps involving heating of a semiconductor substrate, such as various insulation film and conductive film deposition steps) after deposition of the silicon nitride film, the metal silicide layer partially abnormally grows due to oxygen of the natural oxide film occurring on the metal silicide layer surface. A substantially non-bias (including low bias) plasma treatment is performed in a gas atmosphere containing an inert gas as a main component on the top surface of a metal silicide film of nickel silicide or the like over source/drain of a field-effect transistor forming an integrated circuit. Then, a silicon nitride film serving as an etching stop film of a contact process is deposited. As a result, without causing undesirable cutting of the metal silicide film, the natural oxide film over the top surface of the metal silicide film can be removed.Type: ApplicationFiled: November 20, 2009Publication date: May 27, 2010Inventors: Takuya FUTASE, Shuhei MURATA, Takeshi HAYASHI
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Patent number: 7700448Abstract: The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed, n+ type semiconductor region and p+ type semiconductor region for source/drains are formed, a metallic film is formed on a semiconductor substrate, and a barrier film is formed on a metallic film. And after forming the metal silicide layer to which a metallic film, and a gate electrode, n+ type semiconductor region and p+ type semiconductor region are made to react by performing first heat treatment, a barrier film, and an unreacted metallic film are removed, and the metal silicide layer is left. An element isolation region makes compressive stress act on a semiconductor substrate.Type: GrantFiled: January 15, 2008Date of Patent: April 20, 2010Assignee: Renesas Technology Corp.Inventors: Takuya Futase, Keiichiro Kashihara, Shigenari Okada