Patents by Inventor Takuya Futase

Takuya Futase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100093139
    Abstract: To provide a semiconductor device with improved reliability which includes a metal silicide layer formed by a salicide process. After forming gate electrodes, an n+-type semiconductor region, and a p+-type semiconductor region for a source or drain, a Ni1?xPtx alloy film is formed over a semiconductor substrate. The alloy film reacts with the gate electrodes, the n+-type semiconductor region, and the p+-type semiconductor region by a first heat treatment to form a metal silicide layer in a (Ni1?yPty)2Si phase. At this time, the first heat treatment is performed at a heat treatment temperature where a diffusion coefficient of Ni is larger than that of Pt. Further, the first heat treatment is performed such that a reacted part of the alloy film remains at the metal silicide layer. This results in y>x. Then, after removing the unreacted part of the alloy film, the metal silicide layer is further subjected to a second heat treatment to form a metal silicide layer in a Ni1?yPtySi phase.
    Type: Application
    Filed: September 20, 2009
    Publication date: April 15, 2010
    Inventor: Takuya FUTASE
  • Publication number: 20090191707
    Abstract: To provide a technique capable of improving the reliability of a semiconductor element and its product yield by reducing the variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate 1, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. Subsequently, after removing the unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of the first thermal treatment is set to 10° C./s or more (for example, 30 to 250° C.
    Type: Application
    Filed: January 23, 2009
    Publication date: July 30, 2009
    Inventors: Shigenari OKADA, Takuya Futase, Yutaka Inaba
  • Patent number: 7566662
    Abstract: Provided is a method of manufacturing a semiconductor device. After a semiconductor wafer is placed over a wafer stage with which a dry cleaning chamber of a film forming apparatus is equipped, dry cleaning treatment is given over the surface of the semiconductor wafer with a reducing gas. Then, the semiconductor wafer is heat treated at a first temperature of from 100 to 150° C. by using a shower head kept at 180° C. The semiconductor wafer is then vacuum-transferred to a heat treatment chamber, wherein the semiconductor wafer is heat treated at a second temperature of from 150 to 400° C. A product remaining over the main surface of the semiconductor wafer is thus removed. The present invention makes it possible to manufacture a semiconductor device having improved reliability and production yield by reducing variations in the electrical properties of a nickel silicide layer.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: July 28, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Takuya Futase, Hideaki Tsugane, Mitsuo Kimoto, Hidenori Suzuki
  • Publication number: 20090149020
    Abstract: A technology is provided which allows, in a coupling portion obtained by burying a conductive material within a coupling hole bored in an insulating film, the removal of a natural oxide film on the surface of a silicide layer which is present at the bottom portion of the coupling hole. A coupling hole is bored in an interlayer insulating film (first and second insulating films) to expose the surface of a nickel silicide layer at the bottom portion of the coupling hole. Then, reduction gases including a HF gas and a NH3 gas is supplied to the principal surface of a semiconductor wafer to form a product by a reduction reaction, and remove the natural oxide film on the surface of the nickel silicide layer. At this time, the flow rate ratio (HF/NH3 gas flow rate ratio) between the NF gas and the NH3 gas is adjusted to be more than 1 and not more than 5. Preferably, the temperature of the semiconductor wafer is adjusted to be not more than 30° C. Thereafter, a heating process is performed at 400° C.
    Type: Application
    Filed: December 4, 2008
    Publication date: June 11, 2009
    Inventors: Takeshi HAYASHI, Takuya Futase
  • Publication number: 20090011566
    Abstract: After gate insulating films, gate electrodes, and n+ type semiconductor regions and p+ type semiconductor regions for source/drain are formed, a metal film and a barrier film are formed on a semiconductor substrate. And a first heat treatment is performed so as to make the metal film react with the gate electrodes, the n+ type semiconductor region, and the p+ type semiconductor region, thereby forming a metal silicide layer formed of a monosilicide of a metal element forming the metal film. After that, the barrier film and the unreacted metal film are removed, and then a second heat treatment is performed to stabilize the metal silicide layer. The heat treatment temperature is made lower than a temperature at which a lattice size of a disilicide of the metal element and that of the semiconductor substrate become same.
    Type: Application
    Filed: July 3, 2008
    Publication date: January 8, 2009
    Inventors: Shigenari Okada, Takuya Futase
  • Publication number: 20090011597
    Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).
    Type: Application
    Filed: September 10, 2008
    Publication date: January 8, 2009
    Inventors: TAKUYA FUTASE, Tomonori Seaki, Mieko Kashi
  • Publication number: 20080311718
    Abstract: The present invention is to possible to avoid an inconvenience at a coupling portion between a barrier metal film obtained by depositing a titanium nitride film on a titanium film and thus having a film stack structure and a metal film filled, via the barrier metal film, in a connecting hole opened in an insulating film.
    Type: Application
    Filed: June 4, 2008
    Publication date: December 18, 2008
    Inventor: Takuya FUTASE
  • Publication number: 20080242035
    Abstract: The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed, n+ type semiconductor region and p+ type semiconductor region for source/drains are formed, a metallic film is formed on a semiconductor substrate, and a barrier film is formed on a metallic film. And after forming the metal silicide layer to which a metallic film, and a gate electrode, n+ type semiconductor region and p+ type semiconductor region are made to react by performing first heat treatment, a barrier film, and an unreacted metallic film are removed, and the metal silicide layer is left. An element isolation region makes compressive stress act on a semiconductor substrate.
    Type: Application
    Filed: January 15, 2008
    Publication date: October 2, 2008
    Inventors: Takuya FUTASE, Keiichiro Kashihara, Shigenari Okada
  • Publication number: 20080182414
    Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).
    Type: Application
    Filed: January 22, 2008
    Publication date: July 31, 2008
    Inventors: Takuya Futase, Tomonori Saeki, Mieko Kashi
  • Publication number: 20080176396
    Abstract: An object of the invention is to avoid an inconvenience at a connection portion formed by filling a metal film in a connecting hole, which has been opened in an insulating film, via a barrier metal film having a titanium nitride film stacked over a titanium film. A manufacturing method of a semiconductor device has the steps of: forming a thermal reaction Ti film over the bottom of a connecting hole by a thermal reaction using a TiCl4 gas; forming a plasma reaction Ti film by a plasma reaction using a TiCl4 gas; forming a nitrogen-rich TiN film over the surface of the plasma reaction Ti film by plasma treatment with H2 and plasma treatment with NH3 gases; repeatedly carrying out film formation by CVD using a WF6 gas and reduction using an SiH4 or B2H6 gas to form a tungsten nucleation film of a multilayer structure over the nitrogen-rich TiN film; and forming a blanket•tungsten film at 400° C. or less by CVD using WF6 and H2 gases.
    Type: Application
    Filed: October 17, 2007
    Publication date: July 24, 2008
    Inventors: Takuya Futase, Takeshi Hayashi
  • Publication number: 20070269976
    Abstract: To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chamber for dry cleaning treatment of a deposition system, dry cleaning treatment is performed to a principal surface of the semiconductor wafer by supplying reducing gas, sequentially, heat treatment is performed to the semiconductor wafer at a first temperature of 100 to 150° C. by a showerhead which is maintained at 180° C. Next, after the semiconductor wafer is vacuum transferred from the chamber to a chamber for heat treatment, heat treatment is performed to the semiconductor wafer at a second temperature of 150 to 400° C. in the chamber, thereby removing a product remaining over the principal surface of the semiconductor wafer.
    Type: Application
    Filed: May 16, 2007
    Publication date: November 22, 2007
    Inventors: Takuya Futase, Hiroshi Tobimatsu
  • Publication number: 20070238321
    Abstract: Provided is a method of manufacturing a semiconductor device. After a semiconductor wafer is placed over a wafer stage with which a dry cleaning chamber of a film forming apparatus is equipped, dry cleaning treatment is given over the surface of the semiconductor wafer with a reducing gas. Then, the semiconductor wafer is heat treated at a first temperature of from 100 to 150° C. by using a shower head kept at 180° C. The semiconductor wafer is then vacuum-transferred to a heat treatment chamber, wherein the semiconductor wafer is heat treated at a second temperature of from 150 to 400° C. A product remaining over the main surface of the semiconductor wafer is thus removed. The present invention makes it possible to manufacture a semiconductor device having improved reliability and production yield by reducing variations in the electrical properties of a nickel silicide layer.
    Type: Application
    Filed: April 10, 2007
    Publication date: October 11, 2007
    Inventors: Takuya Futase, Hideaki Tsugane, Mitsuo Kimoto, Hidenori Suzuki
  • Publication number: 20040259300
    Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).
    Type: Application
    Filed: March 9, 2004
    Publication date: December 23, 2004
    Applicants: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takuya Futase, Tomonori Saeki, Mieko Kashi
  • Patent number: 6737221
    Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: May 18, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takuya Futase, Tomonori Saeki, Mieko Kashi
  • Publication number: 20030207214
    Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).
    Type: Application
    Filed: April 29, 2003
    Publication date: November 6, 2003
    Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takuya Futase, Tomonori Saeki, Mieko Kashi
  • Patent number: 6586161
    Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: July 1, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takuya Futase, Tomonori Saeki, Mieko Kashi
  • Publication number: 20030017419
    Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).
    Type: Application
    Filed: September 18, 2002
    Publication date: January 23, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Takuya Futase, Tomonori Saeki, Mieko Kashi