Patents by Inventor Takuya Kadoguchi

Takuya Kadoguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10950526
    Abstract: A semiconductor device may include a first conductor plate, a first semiconductor element that is a sole semiconductor element disposed on a main surface of the first conductor plate, an encapsulant encapsulating the first semiconductor element and a first power terminal connected to the first conductor plate within the encapsulant and projecting from the encapsulant along a first direction. The main surface of the first conductor plate may include a first side located close to the first power terminal and a second side located opposite the first side with respect to the first direction. With respect to the first direction, a distance from the first semiconductor element to the first side may be larger than a distance from the first semiconductor element to the second side.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: March 16, 2021
    Assignee: DENSO CORPORATION
    Inventors: Takuya Kadoguchi, Satoshi Takahagi
  • Publication number: 20200365498
    Abstract: A semiconductor device may be provided with: a semiconductor chip; an encapsulant encapsulating the semiconductor chip therein; and a conductor member joined to the semiconductor chip via a solder layer within the encapsulant. The conductor member may comprise a joint surface in contact with the solder layer and a side surface extending from a peripheral edge of the joint surface. The side surface may comprise an unroughened area and a roughened area that is greater in surface roughness than the unroughened area. The unroughened area may be located adjacent to the peripheral edge of the joint surface.
    Type: Application
    Filed: April 3, 2020
    Publication date: November 19, 2020
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takanori Kawashima, Takuya Kadoguchi, Kohji Uramoto, Yasuhiro Ogawa
  • Publication number: 20200365490
    Abstract: A semiconductor device may include: an upper conductive plate, a middle conductive plate, and a lower conductive plate which are stacked on each other; a first semiconductor chip located between the upper and middle conductive plates and electrically connected to both the upper and middle; a second semiconductor chip located between the middle and lower conductive plates and electrically connected to both the middle and lower conductive plates; and an encapsulant encapsulating the first and second semiconductor chips and integrally holding the upper, middle and lower conductive plates. The middle conductive plate may include a main portion joined to the first and second semiconductor chips within the encapsulant and an exposed portion exposed outside on a surface of the encapsulant. A thickness of the exposed portion may be equal to or greater than a thickness of the main portion.
    Type: Application
    Filed: April 9, 2020
    Publication date: November 19, 2020
    Applicant: Toyota Jidosha Kabushiki Kaisha
    Inventors: Takanori Kawashima, Takuya Kadoguchi, Tetsuya Akino, Yuya Osamura
  • Publication number: 20200227380
    Abstract: A method of manufacturing a semiconductor device which includes a plurality of members including a semiconductor element is provided. The method may include disposing one surface of a first member which is one of the plurality of members and one surface of a second member which is another one of the plurality of members opposite to each other with a tin-based (Sn-based) solder material interposed therebetween, and bonding the first member and the second member by melting and solidifying the Sn-based solder material. At least the one surface of the first member may be constituted of a nickel-based (Ni-based) metal, and at least the one surface of the second member may he constituted of copper (Cu).
    Type: Application
    Filed: December 20, 2019
    Publication date: July 16, 2020
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Takuya KADOGUCHI
  • Publication number: 20200203252
    Abstract: A semiconductor device may include a substrate constituted of an insulator; a first conductor film provided on a part of the substrate; a semiconductor chip located on the first conductor film; and an external connection terminal joined to the substrate via a joining layer at a position separated from the first conductor film. The semiconductor chip may be a power semiconductor chip including a main electrode and a signal electrode. The main electrode may be electrically connected to the first conductor film and the signal electrode may be electrically connected to the external connection terminal.
    Type: Application
    Filed: November 25, 2019
    Publication date: June 25, 2020
    Applicant: DENSO CORPORATION
    Inventors: Akinori SAKAKIBARA, Takanori KAWASHIMA, Takuya KADOGUCHI, Kohji URAMOTO, Yasuhiro OGAWA
  • Publication number: 20200091042
    Abstract: A semiconductor device may include a first conductor plate, a first semiconductor element that is a sole semiconductor element disposed on a main surface of the first conductor plate, an encapsulant encapsulating the first semiconductor element and a first power terminal connected to the first conductor plate within the encapsulant and projecting from the encapsulant along a first direction. The main surface of the first conductor plate may include a first side located close to the first power terminal and a second side located opposite the first side with respect to the first direction. With respect to the first direction, a distance from the first semiconductor element to the first side may be larger than a distance from the first semiconductor element to the second side.
    Type: Application
    Filed: August 19, 2019
    Publication date: March 19, 2020
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takuya KADOGUCHI, Satoshi Takahagi
  • Patent number: 10546760
    Abstract: A method of manufacturing a semiconductor device that includes a resin package sealing a semiconductor element and a pair of metal plates interposing the semiconductor element therebetween, in which each of the pair of metal plates is exposed at corresponding one of both surfaces of the resin package is disclosed. The method may include preparing an assembly in which the semiconductor element is connected to the pair of metal plates; setting the assembly in a cavity of a mold, wherein one metal plate is in contact with a bottom surface of the cavity and a space is provided above the other metal plate; forming the resin package by injecting a molten resin into the cavity so as to cover an upper side of the other metal plate, stopping the injecting of the molten resin with a part of the space on an upper side of the cavity unfilled.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: January 28, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takuya Kadoguchi, Yuuji Hanaki, Atsuko Yamanaka, Shou Funano, Satoshi Takahagi, Shingo Iwasaki
  • Patent number: 10475727
    Abstract: A semiconductor device includes an electrode plate, a metallic member, and solder connecting the metallic member with the electrode plate. On a surface of the electrode plate, a first groove and a group of second grooves are provided. The first groove has first to fourth linear parts. The group of second grooves is arranged within a range surrounded by the first groove, and has end portions on an outer periphery side that are connected with the first groove. The group of second grooves includes first to fourth sets. Each of the sets includes a plurality of second grooves connected with the first to fourth linear parts. When the metallic member is seen in a lamination direction of the electrode plate and the metallic member, an outer peripheral edge of a region of the metallic member, the region being connected with the solder, goes across the first to fourth sets.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: November 12, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoshi Takahagi, Syou Funano, Takuya Kadoguchi, Yuji Hanaki, Shingo Iwasaki, Takanori Kawashima
  • Patent number: 10396008
    Abstract: A semiconductor device includes a first metal plate and a second metal plate which interpose a first semiconductor element therebetween, the first metal plate and the second metal plate being bonded to the first semiconductor element with first soldered portions; and includes a third metal plate and a fourth metal plate which interpose a second semiconductor element therebetween, the third metal plate and the fourth metal plate being bonded to the second semiconductor element with second soldered portions. A first joint provided at an edge of the first metal plate and a second joint provided at an edge of the fourth metal plate are bonded with a third soldered portion. A total sum of thicknesses of the first soldered portions is different from a thickness of the third soldered portion, a solidifying point of the thinner one is higher than a solidifying point of the thicker one.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 27, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoshi Takahagi, Takuya Kadoguchi, Yuji Hanaki, Syou Funano, Shingo Iwasaki, Takanori Kawashima
  • Patent number: 10312211
    Abstract: A method of manufacturing a semiconductor device which includes a first member and a second member joined to the first member includes: a) producing (Cu,Ni)6Sn5 on a Ni film formed on the first member by melting a first Sn—Cu solder containing 0.9 wt % or higher of Cu on the Ni film of the first member; b) producing (Cu,Ni)6Sn5 on a Ni film formed on the second member by melting a second Sn—Cu solder containing 0.9 wt % or higher of Cu on the Ni film of the second member; and c) joining the first member and the second member to each other by melting the first Sn—Cu solder having undergone step a) and the second Sn—Cu solder having undergone step b) so that the first Sn—Cu solder and the second Sn—Cu solder become integrated.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: June 4, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takuya Kadoguchi, Naoya Take
  • Publication number: 20190139874
    Abstract: A semiconductor device includes a first switching element; a second switching element; a first metal member; a second metal member; a first terminal that has a potential on a high potential side; a second terminal that has a potential on a low potential side; a third terminal that has a midpoint potential; and a resin part. A first potential part has potential equal to potential of the first terminal. A second potential part has potential equal to potential of the second terminal. A third potential part has potential equal to potential of the third terminal. A first creepage distance between the first potential part and the second potential part is longer than a minimum value of a second creepage distance between the first potential part and the third potential part and a third creepage distance between the second potential part and the third potential part.
    Type: Application
    Filed: January 4, 2019
    Publication date: May 9, 2019
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Takuya KADOGUCHI, Takahiro HIRANO, Arata HARADA, Tomomi OKUMURA, Keita FUKUTANI, Masayoshi NISHIHATA
  • Publication number: 20190027381
    Abstract: A method of manufacturing a semiconductor device that includes a resin package sealing a semiconductor element and a pair of metal plates interposing the semiconductor element therebetween, in which each of the pair of metal plates is exposed at corresponding one of both surfaces of the resin package is disclosed. The method may include preparing an assembly in which the semiconductor element is connected to the pair of metal plates; setting the assembly in a cavity of a mold, wherein one metal plate is in contact with a bottom surface of the cavity and a space is provided above the other metal plate; forming the resin package by injecting a molten resin into the cavity so as to cover an upper side of the other metal plate, stopping the injecting of the molten resin with a part of the space on an upper side of the cavity unfilled.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 24, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takuya KADOGUCHI, Yuuji HANAKI, Atsuko YAMANAKA, Shou FUNANO, Satoshi TAKAHAGI, Shingo IWASAKI
  • Patent number: 10103090
    Abstract: The semiconductor device includes a semiconductor element, and an electro-conductive first plate-like part electrically connected to a top-face-side electrode of the semiconductor element and including a first joint part projecting from a side face, and an electro-conductive second plate-like part including a second joint part projecting from a side face. A bottom face of the first joint part and a top face of the second joint part face one another, and are electrically connected via an electro-conductive bonding material. A bonding-material-thickness ensuring means is provided in a zone where the bottom face of the first joint part and the top face of the second joint part face one another to ensure a thickness of the electro-conductive bonding material between an upper portion of a front end of the second joint part and the bottom face of the first joint part.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: October 16, 2018
    Assignees: Toyota Jidosha Kabushiki Kaisha, Denso Corporation
    Inventors: Takuya Kadoguchi, Takahiro Hirano, Takanori Kawashima, Keita Fukutani, Tomomi Okumura, Masayoshi Nishihata
  • Patent number: 10103091
    Abstract: A semiconductor device may include: a first and a second semiconductor elements each including electrodes on both surfaces thereof; a first and a second metal plates which interpose the first semiconductor element, the metal plates respectively being bonded to the first semiconductor element via first soldered portions; and a third and a fourth metal plates which interpose the second semiconductor element, the metal plates respectively being bonded to the second semiconductor element via second soldered portions; wherein a first joint is provided at the first metal plate, a second joint is provided at the fourth metal plate, the joints are bonded via a third soldered portion, and a solidifying point of the first soldered portions is higher than a solidifying point of the third soldered portion, and a solidifying point of the second soldered portions is higher than the solidifying point of the third soldered portion.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: October 16, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoshi Takahagi, Syou Funano, Takuya Kadoguchi, Yuji Hanaki, Shingo Iwasaki, Takanori Kawashima
  • Publication number: 20180277462
    Abstract: A semiconductor device includes an electrode plate, a metallic member, and solder connecting the metallic member with the electrode plate. On a surface of the electrode plate, a first groove and a group of second grooves are provided. The first groove has first to fourth linear parts. The group of second grooves is arranged within a range surrounded by the first groove, and has end portions on an outer periphery side that are connected with the first groove. The group of second grooves includes first to fourth sets. Each of the sets includes a plurality of second grooves connected with the first to fourth linear parts. When the metallic member is seen in a lamination direction of the electrode plate and the metallic member, an outer peripheral edge of a region of the metallic member, the region being connected with the solder, goes across the first to fourth sets.
    Type: Application
    Filed: March 16, 2018
    Publication date: September 27, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoshi TAKAHAGI, Syou FUNANO, Takuya KADOGUCHI, Yuji HANAKI, Shingo IWASAKI, Takanori KAWASHIMA
  • Publication number: 20180261532
    Abstract: A semiconductor device may include: a first and a second semiconductor elements each including electrodes on both surfaces thereof; a first and a second metal plates which interpose the first semiconductor element, the metal plates respectively being bonded to the first semiconductor element via first soldered portions; and a third and a fourth metal plates which interpose the second semiconductor element, the metal plates respectively being bonded to the second semiconductor element via second soldered portions; wherein a first joint is provided at the first metal plate, a second joint is provided at the fourth metal plate, the joints are bonded via a third soldered portion, and a solidifying point of the first soldered portions is higher than a solidifying point of the third soldered portion, and a solidifying point of the second soldered portions is higher than the solidifying point of the third soldered portion.
    Type: Application
    Filed: January 11, 2018
    Publication date: September 13, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoshi TAKAHAGI, Syou FUNANO, Takuya KADOGUCHI, Yuji HANAKI, Shingo IWASAKI, Takanori KAWASHIMA
  • Patent number: 10049952
    Abstract: A manufacturing method of a semiconductor module includes: sealing an assembly with resin, the assembly including a semiconductor chip, a heat-dissipation plate on the semiconductor chip, and multiple terminals, such that the resin includes a first surface, a second surface located opposite to the first surface, and a side surface, a groove extends in the side surface from the first surface to the second surface, an inner surface of the groove includes a first tapered surface, and a second tapered surface provided between the first tapered surface and the first surface, the second tapered surface inclining toward the first surface at a greater inclination angle than an inclination angle of the first tapered surface; and cutting the first surface within an area located on a first surface side from a boundary between the first tapered surface and the second tapered surface such that the heat-dissipation plate exposes.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: August 14, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takuya Kadoguchi, Takahiro Hirano, Yuuji Hanaki, Shigeru Hayashida
  • Publication number: 20180218960
    Abstract: A semiconductor device includes a first metal plate and a second metal plate which interpose a first semiconductor element therebetween, the first metal plate and the second metal plate being bonded to the first semiconductor element with first soldered portions; and includes a third metal plate and a fourth metal plate which interpose a second semiconductor element therebetween, the third metal plate and the fourth metal plate being bonded to the second semiconductor element with second soldered portions. A first joint provided at an edge of the first metal plate and a second joint provided at an edge of the fourth metal plate are bonded with a third soldered portion. A total sum of thicknesses of the first soldered portions is different from a thickness of the third soldered portion, a solidifying point of the thinner one is higher than a solidifying point of the thicker one.
    Type: Application
    Filed: December 27, 2017
    Publication date: August 2, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoshi TAKAHAGI, Takuya KADOGUCHI, Yuji HANAKI, Syou FUNANO, Shingo IWASAKI, Takanori KAWASHIMA
  • Patent number: 9960096
    Abstract: In a semiconductor device, a second heat sink and a third heat sink are electrically connected by a joint portion in an alignment direction in which a first switching element and a second switching element are aligned. A second power-supply terminal is disposed in the alignment direction in a region between a first power-supply terminal and an output terminal and between the second heat sink and the third heat sink. In an encapsulation resin body, at least one of a shortest distance between a first potential portion at same potential as the first power-supply terminal and a third potential portion at same potential as the output terminal and a shortest distance between a second potential portion at same potential as the second power-supply terminal and the third potential portion is shorter than a shortest distance between the first potential portion and the second potential portion.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: May 1, 2018
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tomomi Okumura, Takuya Kadoguchi
  • Patent number: 9953905
    Abstract: A semiconductor device includes a substrate, a semiconductor element, a terminal and a solder outflow prevention part. The semiconductor element is fixed on one side of the substrate via a first solder layer. The terminal that is fixed on the one side of the substrate via a second solder layer. The solder outflow prevention part is formed between the semiconductor element and the terminal in the one side of the substrate and is configured to prevent the first solder layer and the second solder layer from outflowing. A distance between the solder outflow prevention part and the semiconductor element is longer than a thickness of the first solder layer.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: April 24, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takuya Kadoguchi, Takanori Kawashima