Patents by Inventor Takuya Nakamura

Takuya Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070132200
    Abstract: A number of embodiments of moveable storage racks and/or partitions that can be installed in existing buildings without the necessity of installing guide rails for them. In addition, the movement may be controlled so that the partitions move either in a parallel fashion or they can be rotated through an arc. The partitions are supported on drive and guide belts that are mounted on the underside thereof and which eliminate the need for the guide rails and spread the weight of the partition over a greater area of the floor so as to permit use in buildings which were not originally designed for such systems.
    Type: Application
    Filed: February 13, 2007
    Publication date: June 14, 2007
    Inventors: Kunio Miyazaki, Tomoyuki Kawano, Ichiro Ikenega, Michihiko Higashinosono, Takuya Nakamura, Hiroyuki Kiyota, Kazuya Tokunaga
  • Patent number: 6744546
    Abstract: A multilevel light-intensity modulating circuit for suppressing the amplitude distortion regarding intermediate levels, caused by the conversion from a multilevel electric signal to a multilevel modulated optical signal. The circuit comprises a section for distributing an input optical carrier into n-channel optical carriers; n light-intensity modulators for modulating intensities of the optical carriers by using input two-level electric signals; a control section for producing a phase difference between the n-channel two-level modulated optical signals; a control section for assigning a different light intensity to each of the n-channel two-level modulated optical signals; and a section for combining the n-channel two-level modulated optical signals obtained via the control sections, and outputting a 2n-level modulated optical signal. The phase difference and the different light intensity are defined in advance so as to produce the 2n-level modulated optical signal.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: June 1, 2004
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Takuya Nakamura, Jun-ichi Kani, Mitsuhiro Teshima, Noboru Takachio
  • Publication number: 20040035060
    Abstract: A number of embodiments of moveable storage racks and/or partitions that can be installed in existing buildings without the necessity of installing guide rails for them. In addition, the movement may be controlled so that the partitions move either in a parallel fashion or they can be rotated through an arc. The partitions are supported on drive and guide belts that are mounted on the underside thereof and which eliminate the need for the guide rails and spread the weight of the partition over a greater area of the floor so as to permit use in buildings which were not originally designed for such systems.
    Type: Application
    Filed: February 9, 2003
    Publication date: February 26, 2004
    Inventors: Kunio Miyazaki, Tomoyuki Kawano, Takuya Nakamura, Michihiko Higashinozono, Ichiro Ikenaga, Hiroyuki Kiyota, Kazuya Tokunaga
  • Publication number: 20030123122
    Abstract: A multilevel light-intensity modulating circuit for suppressing the amplitude distortion regarding intermediate levels, caused by the conversion from a multilevel electric signal to a multilevel modulated optical signal. The circuit comprises a section for distributing an input optical carrier into n-channel optical carriers; n light-intensity modulators for modulating intensities of the optical carriers by using input two-level electric signals; a control section for producing a phase difference between the n-channel two-level modulated optical signals; a control section for assigning a different light intensity to each of the n-channel two-level modulated optical signals; and a section for combining the n-channel two-level modulated optical signals obtained via the control sections, and outputting a 2n-level modulated optical signal. The phase difference and the different light intensity are defined in advance so as to produce the 2n-level modulated optical signal.
    Type: Application
    Filed: December 17, 2002
    Publication date: July 3, 2003
    Inventors: Takuya Nakamura, Jun-ichi Kani, Mitsuhiro Teshima, Noboru Takachio
  • Patent number: 6413809
    Abstract: A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: July 2, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuya Nakamura, Naoki Koido, Hirohisa Iizuka, Kazuhito Narita, Seiichi Aritome, Fumitaka Arai
  • Publication number: 20010018253
    Abstract: A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.
    Type: Application
    Filed: March 8, 2001
    Publication date: August 30, 2001
    Inventors: Takuya Nakamura, Naoki Koido, Hirohisa Iizuka, Kazuhito Narita, Seiichi Aritome, Fumitaka Arai
  • Publication number: 20010005521
    Abstract: A powder grain processing apparatus is provided such that both agitation and mixture of powder grains can be performed efficiently.
    Type: Application
    Filed: December 21, 2000
    Publication date: June 28, 2001
    Inventors: Narimichi Takei, Takehiko Itou, Takuya Nakamura, Kazuomi Unosawa
  • Patent number: 6222225
    Abstract: A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: April 24, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuya Nakamura, Naoki Koido, Hirohisa Iizuka, Kazuhito Narita, Seiichi Aritome, Fumitaka Arai
  • Patent number: 5847570
    Abstract: A trigger circuit is composed of a frequency multiplying portion which receives an electric signal to be measured and multiplies its repetitive frequency so as to output a multiple signal, a comparing portion which receives this multiple signal and outputs a square wave signal corresponding to its value, and a dividing portion which divides the square wave signal so as to output a trigger signal. Accordingly, even when a noise component is superposed on the electric signal to be measured, a trigger signal having little jitter and a repetitive frequency lower than that of the electric signal to be measured is output. Also, the electric field measuring apparatus in accordance with the present invention comprises this trigger circuit and measures, with a highly accurate timing, the electric field of the object to be measured.
    Type: Grant
    Filed: August 7, 1996
    Date of Patent: December 8, 1998
    Assignee: Hamamatsu Photonics K. K.
    Inventors: Hironori Takahashi, Takuya Nakamura
  • Patent number: 5703491
    Abstract: This invention has as its object to provide a voltage measurement apparatus which has a compact probe unit, and which can perform a measurement in a non-contact manner. The voltage measurement apparatus includes detection means for detecting an electric field generated in a space by a voltage applied to the surface of a device to be measured, light-emitting means for modulating output light by superposing a detected signal obtained from the detection means on a bias current which is supplied to inductively radiate the output light, a constant current source for supplying the bias current to the light-emitting means, extraction means for extracting a signal component of the output light from the light-emitting means, and light-transmission means for guiding the output light from the light-emitting means to the extraction means, and measures the applied voltage to the surface of the device to be measured by bringing the detection means close to the device to be measured in a non-contact manner.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: December 30, 1997
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Takuya Nakamura, Isuke Hirano, Shinichiro Aoshima, Hironori Takahashi, Tsuneyuki Urakami
  • Patent number: 5583444
    Abstract: This invention has as its object to provide a voltage measurement apparatus which has a compact probe unit, and which can perform a measurement in a non-contact manner. The voltage measurement apparatus includes detection means for detecting an electric field generated in a space by a voltage applied to the surface of a device to be measured, light-emitting means for modulating output light by superposing a detected signal obtained from the detection means on a bias current which is supplied to inductively radiate the output light, a constant current source for supplying the bias current to the light-emitting means, extraction means for extracting a signal component of the output light from the light-emitting means, and light-transmission means for guiding the output light from the light-emitting means to the extraction means, and measures the applied voltage to the surface of the device to be measured by bringing the detection means close to the device to be measured in a non-contact manner.
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: December 10, 1996
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Takuya Nakamura, Isuke Hirano, Shinichiro Aoshima, Hironori Takahashi, Tsuneyuki Urakami
  • Patent number: D505362
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: May 24, 2005
    Assignee: Suzuki Motor Corporation
    Inventor: Takuya Nakamura
  • Patent number: D550384
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: September 4, 2007
    Assignee: Yamaha Hatsudoki Kabushiki Kaisha
    Inventors: Hiroshi Shimokawa, Takuya Nakamura
  • Patent number: D550602
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: September 11, 2007
    Assignee: Yamaha Hatsudoki Kabushiki Kaisha
    Inventors: Hiroshi Shimokawa, Takuya Nakamura
  • Patent number: D551365
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: September 18, 2007
    Assignee: Yamaha Hatsudoki Kabushiki Kaisha
    Inventors: Hiroshi Shimokawa, Takuya Nakamura
  • Patent number: D557638
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: December 18, 2007
    Assignee: Yamaha Hatsudoki Kabushiki Kaisha
    Inventors: Takuya Nakamura, Hiroshi Shimokawa
  • Patent number: D559757
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: January 15, 2008
    Assignee: Yamaha Hatsudoki Kabushiki Kaisha
    Inventors: Hiroshi Shimokawa, Takuya Nakamura
  • Patent number: D480334
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: October 7, 2003
    Assignee: Suzuki Motor Corporation
    Inventor: Takuya Nakamura
  • Patent number: D561703
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: February 12, 2008
    Assignee: Yamaha Hatsudoki Kabushiki Kaisha
    Inventors: Hiroshi Shimokawa, Takuya Nakamura
  • Patent number: D414721
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: October 5, 1999
    Assignee: Suzuki Motor Corporation
    Inventor: Takuya Nakamura