Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: An insertion layer for perpendicular spin orbit torque (SOT) memory devices between the SOT electrode and the free magnetic layer, memory devices and computing platforms employing such insertion layers, and methods for forming them are discussed. The insertion layer is predominantly tungsten and improves thermal stability and perpendicular magnetic anisotropy in the free magnetic layer.

Abstract: An apparatus is provided to improve spin injection efficiency from a magnet to a spin orbit coupling material. The apparatus comprises: a first magnet; a second magnet adjacent to the first magnet; a first structure comprising a tunneling barrier; a third magnet adjacent to the first structure; a stack of layers, a portion of which is adjacent to the third magnet, wherein the stack of layers comprises spin-orbit material; and a second structure comprising magnetoelectric material, wherein the second structure is adjacent to the first magnet.

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: An apparatus is provided which comprises: a first stack comprising a magnetic insulating material (MI such as, EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene; a second stack comprising an MI material and a TMD, wherein the first and second stacks are separated by an insulating material (e.g., oxide); a magnet (e.g., a ferromagnet or a paramagnet) adjacent to the TMDs of the first and second stacks, and also adjacent to the insulating material; and a magnetoelectric material (e.g., (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, or (SmBi)FeO3) adjacent to the magnet.

Abstract: An apparatus is provided which comprises: a magnetic junction including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device; a second structure comprising one of a dielectric or metal; a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure comprising an antiferromagnetic (AFM) material, the fourth structure adjacent to the third structure; a fifth structure comprising a magnet with PMA, the fifth structure adjacent to the fourth structure; and an interconnect adjacent to the first structure, the interconnect comprising spin orbit material.

Abstract: An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.

Abstract: Spin orbit torque (SOT) devices with topological insulator (TI) and heavy metal insert are described. In an example, an integrated circuit structure includes a spin orbit coupling (SOC) interconnect including a TI material. A magnetic layer is above the SOC interconnect. An insert layer includes a heavy metal between and in contact with the TI material and the magnetic layer.

Abstract: A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.

Abstract: A multilayer free magnetic layer structure for spin-based magnetic memory is provided herein. The multilayer free magnetic structure is employed in a magnetic tunnel junction (MTJ) and includes antiferromagnetically coupled magnetic layers. In some cases, the antiferromagnetic coupling is mediated by RKKY interaction with a Ru, Ir, Mo, Cu, or Rh spacer layer. In some cases, low damping magnetic materials, such as CoFeB, FeB, or CoFeBMo are used for the antiferromagnetically coupled magnetic layers. By employing the multilayer free magnetic structure for the MTJ as variously described herein, the critical or switching current can be significantly reduced compared to, for example, an MTJ employing a single-layer free magnetic layer. Thus, higher device efficiencies can be achieved. In some cases, the magnetic layers of the multilayer free magnetic structure are perpendicular magnets, which can be employed, for example, in perpendicular spin-orbit torque (pSOT) memory devices.

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: Embodiments herein relate to magnetically doping a spin orbit torque electrode (SOT) in a magnetic random access memory apparatus. In particular, the apparatus may include a free layer of a magnetic tunnel junction (MTJ) coupled to a SOT electrode that is magnetically doped to apply an effective magnetic field on the free layer, where the free layer has a magnetic polarization in a first direction and where current flowing through the magnetically doped SOT electrode is to cause the magnetic polarization of the free layer to change to a second direction that is substantially opposite to the first direction.

Abstract: An apparatus is provided which comprises: a magnetic junction (e.g., a magnetic tunneling junction or spin valve). The apparatus further includes a structure (e.g., an interconnect) comprising spin orbit material, the structure adjacent to the magnetic junction; first and second transistors. The first transistor is coupled to a bit-line and a first word-line, wherein the first transistor is adjacent to the magnetic junction. The second transistor is coupled to a first select-line and a second word-line, wherein the second transistor is adjacent to the structure, wherein the interconnect is coupled to a second select-line, and wherein the magnetic junction is between the first and second transistors.

Abstract: Electrical devices with an integral thermoelectric generator comprising a spin-Seebeck insulator and a spin orbit coupling material, and associated methods of fabrication. A spin-Seebeck thermoelectric material stack may be integrated into macroscale power cabling as well as nanoscale device structures. The resulting structures are to leverage the spin-Seebeck effect (SSE), in which magnons may transport heat from a source (an active device or passive interconnect) and through the spin-Seebeck insulator, which develops a resulting spin voltage. The SOC material is to further convert the spin voltage into an electric voltage to complete the thermoelectric generation process. The resulting electric voltage may then be coupled into an electric circuit.

Abstract: A memory device comprises a substrate having a front side and a backside, wherein a first conductive line is on the backside and a second conductive line is on the front side. A transistor is on the front side between the second conductive line and the substrate. A magnetic tunnel junction (MTJ) is on the backside between the first conductive line and the substrate, wherein one end of the MTJ is coupled through the substrate to the transistor and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to the second conductive line on the front side.

Abstract: An apparatus is provided which comprises: a first stack comprising a magnetic insulating material (MI such as, EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene; a second stack comprising an MI material and a TMD, wherein the first and second stacks are separated by an insulating material (e.g., oxide); a magnet (e.g., a ferromagnet or a paramagnet) adjacent to the TMDs of the first and second stacks, and also adjacent to the insulating material; and a magnetoelectric material (e.g., (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, or (SmBi)FeO3) adjacent to the magnet.