Patents by Inventor Tanay A. Gosavi

Tanay A. Gosavi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200212291
    Abstract: A memory device comprises an interconnect comprises a spin orbit coupling (SOC) material. A free magnetic layer is on the interconnect, a barrier material is over the free magnetic layer and a fixed magnetic layer is over the barrier material, wherein the free magnetic layer comprises an antiferromagnet. In another embodiment, memory device comprises a spin orbit coupling (SOC) interconnect and an antiferromagnet (AFM) free magnetic layer is on the interconnect. A ferromagnetic magnetic tunnel junction (MTJ) device is on the AFM free magnetic layer, wherein the ferromagnetic MTJ comprises a free magnet layer, a fixed magnet layer, and a barrier material between the free magnet layer and the fixed magnet layer.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Chia-Ching LIN, Sasikanth MANIPATRUNI, Tanay GOSAVI, Dmitri NIKONOV, Kaan OGUZ, Ian A. YOUNG
  • Publication number: 20200194576
    Abstract: Embodiments disclosed herein include transistor devices with complex oxide interfaces and methods of forming such devices. In an embodiment, the transistor device may comprise a substrate, and a fin extending up from the substrate. In an embodiment, a first oxide is formed over sidewall surfaces of the fin, and a second oxide is formed over the first oxide. In an embodiment, the first oxide and the second oxide are perovskite oxides with the general formula of ABO3.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: Sasikanth MANIPATRUNI, Dmitri NIKONOV, Chia-Ching LIN, Tanay GOSAVI, Uygar AVCI, Ian YOUNG
  • Publication number: 20200194444
    Abstract: An embodiment includes a system comprising: first, second, third, fourth, fifth, and sixth layers, (a) the second, third, fourth, and fifth layers being between the first and sixth layers, and (b) the fourth layer being between the third and fifth layers; a formation between the first and second layers, the formation including: (a) a material that is non-amorphous; and (b) first and second sidewalls; a capacitor between the second and sixth layers, the capacitor including: (a) the third, fourth, and fifth layers, and (b) an electrode that includes the third layer and an additional electrode that includes the fifth layer; and a switching device between the first and sixth layers; wherein: (a) the first layer includes a metal and the sixth layer includes the metal, and (b) the fourth layer includes a Perovskite material. Other embodiments are addressed herein.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 18, 2020
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Tanay Gosavi, Dmitri Nikonov, Sou-Chi Chang, Uygar E. Avci, Ian A. Young
  • Publication number: 20200162024
    Abstract: Embodiments may relate to a piezoresistive oscillator. The oscillator may include a fin field-effect transistor (FinFET) with a source electrode, a drain electrode, and a gate electrode. The oscillator may further include an electrical coupling coupled with the FinFET, wherein the electrical coupling electrically couples the gate electrode to the source electrode or the drain electrode. Other embodiments may be described or claimed.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Applicant: Intel Corporation
    Inventors: Dmitri E. Nikonov, Raseong Kim, Sasikanth Manipatruni, Ian A. Young, Gary Alfred Allen, Tanay Gosavi
  • Publication number: 20200161535
    Abstract: A memory apparatus is provided which comprises: a stack comprising a magnetic insulating material and a transition metal dichalcogenide (TMD), wherein the magnetic insulating material has a first magnetization. The stack behaves as a free magnet. The apparatus includes a fixed magnet with a second magnetization. An interconnect is further provided which comprises a spin orbit material, wherein the interconnect is adjacent to the stack.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching LIN, Tanay GOSAVI, Sasikanth MANIPATRUNI, Dmitri NIKONOV, Ian YOUNG
  • Publication number: 20200098410
    Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device. In some embodiments, the apparatus comprises an interconnect partially adjacent to the structure of the magnetic junction, wherein the interconnect comprises a spin orbit material, wherein the interconnect has a pocket comprising non-spin orbit material, wherein the pocket is adjacent to the magnet of the magnetic junction. In some embodiments, the non-spin orbit material comprises metal which includes one or more of: Cu, Al, Ag, or Au.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Applicant: Inte Corporation
    Inventors: Tanay Gosavi, Sasikanth Manipatruni, Chia-Ching Lin, Dmitri Nikonov, Christopher Wiegand, Ian Young
  • Publication number: 20200083284
    Abstract: Electrical devices with an integral thermoelectric generator comprising a spin-Seebeck insulator and a spin orbit coupling material, and associated methods of fabrication. A spin-Seebeck thermoelectric material stack may be integrated into macroscale power cabling as well as nanoscale device structures. The resulting structures are to leverage the spin-Seebeck effect (SSE), in which magnons may transport heat from a source (an active device or passive interconnect) and through the spin-Seebeck insulator, which develops a resulting spin voltage. The SOC material is to further convert the spin voltage into an electric voltage to complete the thermoelectric generation process. The resulting electric voltage may then be coupled into an electric circuit.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 12, 2020
    Applicant: Intel Corporation
    Inventors: Sasikanth Manipatruni, Tanay Gosavi, Dmitri Nikonov, Ian Young
  • Publication number: 20200083427
    Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 12, 2020
    Applicant: Intel Corporation
    Inventors: Sasikanth MANIPATRUNI, Kaan OGUZ, Chia-Ching LIN, Christopher WIEGAND, Tanay GOSAVI, Ian YOUNG
  • Publication number: 20200083286
    Abstract: An apparatus is provided which comprises: a magnetic junction (e.g., a magnetic tunneling junction or spin valve). The apparatus further includes a structure (e.g., an interconnect) comprising spin orbit material, the structure adjacent to the magnetic junction; first and second transistors. The first transistor is coupled to a bit-line and a first word-line, wherein the first transistor is adjacent to the magnetic junction. The second transistor is coupled to a first select-line and a second word-line, wherein the second transistor is adjacent to the structure, wherein the interconnect is coupled to a second select-line, and wherein the magnetic junction is between the first and second transistors.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 12, 2020
    Inventors: Sasikanth Manipatruni, Christopher Wiegand, Tanay Gosavi, Ian Young
  • Publication number: 20200006631
    Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a magnetic tunnel junction (MTJ) device on a portion of the electrode. The electrode has a first SOC layer and a second SOC layer on a portion of the first SOC layer, where at least a portion of the first SOC layer at an interface with the second SOC layer includes oxygen.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Noriyuki Sato, Tanay Gosavi, Justin Brockman, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Christopher Wiegand, Angeline Smith, Tofizur Rahman, Ian Young
  • Publication number: 20200006636
    Abstract: Embodiments herein relate to magnetically doping a spin orbit torque electrode (SOT) in a magnetic random access memory apparatus. In particular, the apparatus may include a free layer of a magnetic tunnel junction (MTJ) coupled to a SOT electrode that is magnetically doped to apply an effective magnetic field on the free layer, where the free layer has a magnetic polarization in a first direction and where current flowing through the magnetically doped SOT electrode is to cause the magnetic polarization of the free layer to change to a second direction that is substantially opposite to the first direction.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Tanay GOSAVI, Sasikanth MANIPATRUNI, Chia-Ching LIN, Gary ALLEN, Kaan OGUZ, Kevin O?BRIEN, Noriyuki SATO, Ian YOUNG, Dmitri NIKONOV
  • Publication number: 20200006637
    Abstract: Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Tanay GOSAVI, Sasikanth MANIPATRUNI, Chia-Ching LIN, Kaan OGUZ, Christopher WIEGAND, Angeline SMITH, Noriyuki SATO, Kevin O'BRIEN, Benjamin BUFORD, Ian YOUNG, MD Tofizur RAHMAN
  • Publication number: 20200006643
    Abstract: Embodiments herein relate to manufacturing a magnetic random access memory (MRAM). In particular, a process may include coupling a side of a magnetic free layer of a magnetic tunnel junction (MTJ) to a first side of a hybrid spin orbit torque (SOT) electrode-insert layer, coupling a first side of an atomic layer etching (ALE) etch layer to a second side of the hybrid SOT electrode-insert layer opposite the first side, applying an interlayer dielectric (ILD) layer to edges of the MTJ, the SOT electrode and the etch layers, the ILD layer in a plane substantially perpendicular to a plane of the MTJ, SOT electrode and ALE etch layers, and etching the ALE etch layer using ALE until the SOT layer is exposed.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Tanay GOSAVI, Sasikanth MANIPATRUNI, Chia-Ching LIN, Gary ALLEN, Scott B. CLENDENING, Ian YOUNG
  • Publication number: 20200006424
    Abstract: A spin orbit torque (SOT) memory device includes a magnetic tunnel junction (MTJ) device with one end coupled with a first electrode and an opposite end coupled with a second electrode including a spin orbit torque material. In an embodiment, a second electrode is coupled with the free magnet and coupled between a pair of interconnect line segments. The second electrode and the pair of interconnect line segments include a spin orbit torque material. The second electrode has a conductive path cross-section that is smaller than a cross section of the conductive path in at least one of the interconnect line segments.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Noriyuki Sato, Angeline Smith, Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Tofizur Rahman, Gary Allen, Atm G. Sarwar, Ian Young, Hui Jae Yoo, Christopher Weigand, Benjamin Buford
  • Publication number: 20200006627
    Abstract: A memory device comprises a substrate having a front side and a backside, wherein a first conductive line is on the backside and a second conductive line is on the front side. A transistor is on the front side between the second conductive line and the substrate. A magnetic tunnel junction (MTJ) is on the backside between the first conductive line and the substrate, wherein one end of the MTJ is coupled through the substrate to the transistor and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to the second conductive line on the front side.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Sasikanth MANIPATRUNI, Tanay GOSAVI, Ian YOUNG, Dmitri NIKONOV
  • Publication number: 20200006625
    Abstract: A multilayer free magnetic layer structure for spin-based magnetic memory is provided herein. The multilayer free magnetic structure is employed in a magnetic tunnel junction (MTJ) and includes antiferromagnetically coupled magnetic layers. In some cases, the antiferromagnetic coupling is mediated by RKKY interaction with a Ru, Ir, Mo, Cu, or Rh spacer layer. In some cases, low damping magnetic materials, such as CoFeB, FeB, or CoFeBMo are used for the antiferromagnetically coupled magnetic layers. By employing the multilayer free magnetic structure for the MTJ as variously described herein, the critical or switching current can be significantly reduced compared to, for example, an MTJ employing a single-layer free magnetic layer. Thus, higher device efficiencies can be achieved. In some cases, the magnetic layers of the multilayer free magnetic structure are perpendicular magnets, which can be employed, for example, in perpendicular spin-orbit torque (pSOT) memory devices.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: KAAN OGUZ, TANAY GOSAVI, SASIKANTH MANIPATRUNI, CHIA-CHING LIN, GARY ALLEN
  • Publication number: 20200006630
    Abstract: A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Noriyuki Sato, Tanay Gosavi, Gary Allen, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Christopher Wiegand, Angeline Smith, Tofizur Rahman, Ian Young, Ben Buford
  • Publication number: 20200006626
    Abstract: An insertion layer for perpendicular spin orbit torque (SOT) memory devices between the SOT electrode and the free magnetic layer, memory devices and computing platforms employing such insertion layers, and methods for forming them are discussed. The insertion layer is predominantly tungsten and improves thermal stability and perpendicular magnetic anisotropy in the free magnetic layer.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Angeline Smith, Ian Young, Kaan Oguz, Sasikanth Manipatruni, Christopher Wiegand, Kevin O'Brien, Tofizur Rahman, Noriyuki Sato, Benjamin Buford, Tanay Gosavi
  • Publication number: 20190386202
    Abstract: A low power, energy efficient, nonvolatile, high-speed memory apparatus is provided that can function at extremely low temperatures (e.g., less than 30 degree Kelvin). The apparatus includes: a first structure comprising a magnet having free or unpinned magnetization; a second structure comprising Type-II multiferroic material, wherein the second structure is adjacent to the first structure; and an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the first structure.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 19, 2019
    Applicant: Intel Corporation
    Inventors: Tanay Gosavi, Chia-Ching Lin, Sasikanth Manipatruni, Dmitri Nikonov, Ian Young
  • Publication number: 20190386208
    Abstract: An apparatus is provided which comprises: a stack comprising a magnetoelectric (ME such as BiFeO3, (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, SmBiFeO3, Cr2O3, etc.) material and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, graphene, etc.); a magnet adjacent to a first portion of the TMD of the stack; a first interconnect adjacent to the magnet; a second interconnect adjacent to the ME material of the stack; and a third interconnect adjacent to a second portion of the TMD of the stack.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 19, 2019
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Tanay Gosavi, Dmitri Nikonov, Benjamin Buford, Kaan Oguz, John J. Plombon, Ian A. Young