Patents by Inventor Tanay Karnik

Tanay Karnik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power management integrated circuit
    Patent number: 7671456
    Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, James W. Tschantz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Delay fault detection using latch with error sampling
    Patent number: 7653850
    Abstract: Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: January 26, 2010
    Assignee: Intel Corporation
    Inventors: James W. Tschanz, Keith A. Bowman, Nam Sung Kim, Chris Wilkerson, Shih-Lien L. Lu, Tanay Karnik
  • Multi-die integrated circuit device and method
    Publication number: 20090321893
    Abstract: In some embodiments, provided is an integrated circuit with a first die coupled to a second die. The second die has through-silicon vias disposed through it to provide power references to the first die. The through-silicon vias are laterally re-positionable without inhibiting circuit sections in the second die.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventors: Dinesh Somasekhar, Tanay Karnik, Jianping Xu, Yibin Ye
  • Integrated inductor
    Patent number: 7636242
    Abstract: An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: December 22, 2009
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Edward Burton, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Kaladhar Radhakrishnan, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • GROUNDING OF MAGNETIC CORES
    Publication number: 20090267722
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Application
    Filed: April 29, 2009
    Publication date: October 29, 2009
    Inventors: GERHARD SCHROM, DONALD GARDNER, PETER HAZUCHA, FABRICE PAILLET, TANAY KARNIK
  • Signal generating circuit
    Patent number: 7602257
    Abstract: A signal generating circuit is provided. The signal generating circuit may include a plurality of delay circuits coupled to provide a plurality of control signals, a weighted-sum circuit to receive the plurality of control signals and to provide an output analog signal, and a comparator circuit to compare the output analog signal with a voltage and to provide a pulse width modulated (PWM) signal based on the comparison.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: October 13, 2009
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Dinesh Somasekhar, Fabrice Paillet, Peter Hazucha, Sung Tae Moon, Tanay Karnik
  • SLOTTED MAGNETIC MATERIAL FOR INTEGRATED CIRCUIT INDUCTORS
    Publication number: 20090207576
    Abstract: An embodiment is an inductor that may include a slotted magnetic material to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.
    Type: Application
    Filed: March 18, 2009
    Publication date: August 20, 2009
    Applicant: INTEL CORPORATION
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Power Delivery System
    Publication number: 20090199033
    Abstract: A system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load a power supply, a load coupled to the power supply to receive one or more voltages from the power supply, and a digital bus, coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load.
    Type: Application
    Filed: January 20, 2009
    Publication date: August 6, 2009
    Inventors: Shekhar Borkar, Tanay Karnik, Peter Hazucha, Gerhard Schrom, Greg Dermer
  • Power delivery and power management of many-core processors
    Patent number: 7568115
    Abstract: According to embodiments of the disclosed subject matter in this application, a power management system with multiple voltage regulator (“VRs”) may be used to supply power to cores in a many-core processor. Each VR may supply power to a core or a part of a core. Different VRs may provide multiple voltages to a core/part in the many-core processor. The value of the output voltage of a VR may be modulated under the direction of the core/part to which the voltage regulator supplies power. In one embodiment, the multiple VRs may be integrated with cores in a single die. In another embodiment, the power management system with multiple VRs may be on a die (“the VR die”) separate from the die of the many-core processor. The VR die may be included in the same package as the many-core processor die.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: July 28, 2009
    Assignee: Intel Corporation
    Inventors: Shekhar Borkar, Tanay Karnik, Shu-ling Garver
  • MULTIPHASE TRANSFORMER FOR A MULTIPHASE DC-DC CONVERTER
    Publication number: 20090174377
    Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
    Type: Application
    Filed: March 16, 2009
    Publication date: July 9, 2009
    Inventors: Gerhard Schrom, Peter Hazucha, Jaeseo Lee, Fabrice Paillet, Tanay Karnik, Vivek De
  • FORMING INDUCTOR AND TRANSFORMER STRUCTURES WITH MAGNETIC MATERIALS USING DAMASCENE PROCESSING FOR INTEGRATED CIRCUITS
    Publication number: 20090166804
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Applicant: INTEL CORPORATION
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Reducing minimum operating voltage through hybrid cache design
    Publication number: 20090172283
    Abstract: Methods and apparatus to reduce minimum operating voltage through a hybrid cache design are described. In one embodiment, a cache with different size bit cells may be used, e.g., to reduce minimum operating voltage of an integrated circuit device that includes the cache and possibly other logic (such as a processor). Other embodiments are also described.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Muhammad M. Khellah, Christopher Wilkerson, Alaa R. Alameldeen, Bibiche M. Geuskens, Tanay Karnik, Vivek De, Gunjan H. Pandya
  • Grounding of magnetic cores
    Patent number: 7538653
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Donald Gardner, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Optical offset signal cancellation for optical receiver
    Patent number: 7536107
    Abstract: A laser driver for high speed interconnections may convert a digital signal to a current train of a bias mode to represent logical zero and of a modulation mode to represent logical one. An optical signal thus produced may include an optical offset. An optical receiver may include a photo-detector to receive the optical signal and generate a current signal, which includes a corresponding current offset. A first amplifier stage converts the current signal to a voltage signal and a second amplifier stage generates a digital output from the voltage signal. One or more low-pass filters may be used to filter the digital output and generate a filtered offset signal for a differential amplifier to generate an offset cancellation signal. The offset cancellation signal may be provided to offset cancellation circuitry to remove the current offset from the current signal generated by the photo-detector.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Fabrice Paillet, Tanay Karnik, Jianping Xu, Donald S. Gardner
  • METHODS OF FORMING MAGNETIC VIAS TO MAXIMIZE INDUCTANCE IN INTEGRATED CIRCUITS AND STRUCTURES FORMED THEREBY
    Publication number: 20090117325
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of a magnetic material on a substrate, forming an oxide layer on the first layer of the magnetic material, forming at least one conductive structure on the first magnetic layer, forming a dielectric layer on the at least one conductive structure, forming a second layer of the magnetic material on the at least one conductive structure, and forming a magnetic via coupled to the first and second layers of the magnetic material, wherein the magnetic via comprises a shape to increase inductance of the inductive structure.
    Type: Application
    Filed: November 7, 2007
    Publication date: May 7, 2009
    Inventors: Donald Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • 0th droop detector architecture and implementation
    Patent number: 7528619
    Abstract: A voltage droop detector captures the very high-frequency noise on the power grid of a load, such as a microprocessor. The droop detector includes twin circuits, one of which receives the voltage from the power grid of the load, the other of which receives a filtered voltage. A 0th droop, as well as 1st droops, 2nd droops, and so on, are captured and stored for subsequent analysis. The circuits sample the voltages frequently enough to ensure that all droop events are captured. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: May 5, 2009
    Assignee: Intel Corporation
    Inventors: Fabrice Paillet, Tanay Karnik, Jianping Xu, Vivek K. De
  • Power delivery system in which power supply and load exchange power consumption measurements via digital bus
    Patent number: 7523337
    Abstract: A system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load a power supply, a load coupled to the power supply to receive one or more voltages from the power supply, and a digital bus, coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: April 21, 2009
    Assignee: Intel Corporation
    Inventors: Shekhar Borkar, Tanay Karnik, Peter Hazucha, Gerhard Schrom, Greg Dermer
  • Slotted magnetic material for integrated circuit inductors
    Patent number: 7518481
    Abstract: An embodiment is an inductor that may include a slotted magnetic material to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: April 14, 2009
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Laser driver for high speed short distance links
    Patent number: 7505497
    Abstract: One embodiment of a laser driver for high speed interconnections includes a buffered level shifter to shift the input voltage level to an appropriate level. In some embodiments the buffered level shifter may be tuned to provide a desired level shift with impedance matched to the driving load. Another embodiment converts a digital signal to a current train of a bias mode to represent logical zero and of a modulation mode to represent logical one, wherein one or both of the bias mode and modulation mode may be adjusted, for example by a programmable control circuit or by an adaptive control circuit. Some embodiments also provide circuitry for reducing overshoot of the output signal.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: March 17, 2009
    Assignee: Intel Corporation
    Inventors: Jianping Xu, Fabrice Paillet, Tanay Karnik
  • Multiphase transformer for a multiphase DC-DC converter
    Patent number: 7504808
    Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: March 17, 2009
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Peter Hazucha, Jaeseo Lee, Fabrice Paillet, Tanay Karnik, Vivek De