Patents by Inventor Tanay Karnik

Tanay Karnik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low-voltage, buffered bandgap reference with selectable output voltage
    Publication number: 20060290415
    Abstract: A temperature-independent voltage reference containing two independent bias circuits powered by the reference voltage, each bias circuit containing components with an exponential dependence of current on voltage and one containing a resistive impedance, and further including voltage dividers and an active component.
    Type: Application
    Filed: June 28, 2005
    Publication date: December 28, 2006
    Inventors: Peter Hazucha, Sung Moon, Gerhard Schrom, Fabrice Paillet, Tanay Karnik, Vivek De
  • Voltage regulation using digital voltage control
    Publication number: 20060290547
    Abstract: For one disclosed embodiment, error is sensed in a voltage at an output node. One or more analog signals are generated based on the sensed error. One or more generated analog signals are converted into one or more digital signals. The voltage at the output node is controlled in response to the one or more digital signals.
    Type: Application
    Filed: June 27, 2005
    Publication date: December 28, 2006
    Inventors: Peter Hazucha, Saravanan Rajapandian, Gerhard Schrom, Tanay Karnik, Vivek De
  • Memory cell driver circuits
    Publication number: 20060291265
    Abstract: A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.
    Type: Application
    Filed: June 27, 2005
    Publication date: December 28, 2006
    Inventors: Gerhard Schrom, Fabrice Paillet, Tanay Karnik, Dinesh Somasekhar, Yibin Ye, Ali Keshavarzi, Muhammad Khellah, Vivek De
  • APPARATUS AND METHOD FOR PROGRAMMING A MEMORY ARRAY
    Publication number: 20060285393
    Abstract: A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.
    Type: Application
    Filed: June 21, 2005
    Publication date: December 21, 2006
    Inventors: Fabrice Paillet, Ali Keshavarzi, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De, Tanay Karnik
  • Power transformer
    Publication number: 20060273872
    Abstract: A multi-phase transformer is provided that includes a first layer having at least a first planar wire and a second planar wire and a second layer formed on the first layer and having at least a third planar wire and a fourth planar wires. At least the first planar wire and the second planar wire of the first layer to form two transformers with at least two planar wires of the second layer. The multi-phase transformer may also include a coupling device to couple one end of the planar wires of the first layer with one of the planar wires of the second layer.
    Type: Application
    Filed: June 1, 2005
    Publication date: December 7, 2006
    Inventors: Peter Hazucha, Gerhard Schrom, Weimin Shi, Edward Burton, Trang Nguyen, Bradley Bloechel, Mary Bloechel, Tanay Karnik
  • Signal measurement systems and methods
    Publication number: 20060220677
    Abstract: Systems and methods are disclosed for measuring signals on an integrated circuit die. In one embodiment, a reference signal is distributed to die locations proximal to the signals to be measured. The reference signal is transmitted over transport paths coupling each of the signals to be measured to the die output. The signals to be measured are transmitted over their respective transport paths and measured at the die output. The relative delay between the signals can be calculated using the reference signal measurements.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Applicant: Intel Corporation, A DELAWARE CORPORATION
    Inventors: Peter Hazucha, Gerhard Schrom, Tanay Karnik, Vivek De
  • Programmable current load systems and methods
    Publication number: 20060224337
    Abstract: One disclosed system includes a plurality of current sink elements coupled between a power supply and a reference potential. A plurality of multiplexers are configured to enable the current sink elements to sink current, and a plurality of selection inputs are configured to control the state of the multiplexers.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Applicant: Intel Corporation, A DELAWARE CORPORATION
    Inventors: Peter Hazucha, Gerhard Schrom, Tanay Karnik
  • Magnetic material for transformers and/or inductors
    Patent number: 7098766
    Abstract: A transformer is provided that includes a plurality of metal lines and a magnetic material provided about the plurality of metal lines. The magnetic material may include a structure to reduce Eddy currents flowing in the magnetic material. This structure may be a plurality of slots extending perpendicular to the metal lines. This structure may also be a laminated structure.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: August 29, 2006
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Vivek K. De
  • Symmetric and non-stacked XOR circuit
    Patent number: 7088138
    Abstract: A CML XOR logic circuit is provided that includes a pair of pull-up transistors, a pair of current source transistors and a logic switch network coupled between the pull-up transistors and the current source transistors. The logic switch network including a plurality of transistors divided into a first branch, a second branch and a third branch. A tail current flows through the first branch, the second branch or the third branch based on at least two input signals to the plurality of transistors.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: August 8, 2006
    Assignee: Intel Corporation
    Inventors: Jianping Xu, Fabrice Paillet, Tanay Karnik
  • Delay interpolation in a ring oscillator delay stage
    Patent number: 7088191
    Abstract: According to some embodiments, a circuit includes a delay stage of a ring oscillator. The delay stage may include a first differential pair, a second differential pair, and a third differential pair. The first differential pair may be coupled to a first current-steering circuit, receive a differential input signal, and output a first differential signal. The second differential pair may receive the differential input signal and output a second differential signal, and the third differential pair may be coupled to a second current-steering circuit, receive the second differential signal from the second differential pair, and output the first differential signal. An amount of delay between the differential input signal and the first differential signal is based on relative amounts of current steered by the first current-steering circuit and the second current-steering circuit.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: August 8, 2006
    Assignee: Intel Corporation
    Inventors: Fabrice Paillet, David Rennie, Tanay Karnik, Jianping Xu
  • Low-swing level shifter
    Publication number: 20060170481
    Abstract: In general, in one aspect, the disclosure describes an apparatus for shifting a low swing signal. The apparatus includes a first pair of transistors to receive a first input signal and a second input signal and to generate a first output signal that is a shifted version of the first input signal. The apparatus further includes a second pair of transistors to receive the first input signal and the second input signal and to generate a second output signal that is a shifted version of the second input signal.
    Type: Application
    Filed: January 31, 2005
    Publication date: August 3, 2006
    Inventors: Fabrice Paillet, David Rennie, Tanay Karnik, Jianping Xu
  • Dynamic gate with conditional keeper for soft error rate reduction
    Patent number: 7053663
    Abstract: A dynamic logic gate with a conditional keeper, the conditional keeper comprising a pMOSFET pull-up that switches ON only after the dynamic logic gate completes an evaluation so as to avoid contention with the pull-down network. By sizing the conditional keeper to be stronger than the half-keeper, embodiments may realize a significant reduction in soft error rates that are latched.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: May 30, 2006
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Atila Alvandpour, Ram Krishnamurthy, Tanay Karnik
  • Oscillator delay stage with active inductor
    Publication number: 20060103479
    Abstract: According to some embodiments, a circuit includes a ring oscillator delay stage. The delay stage may include a first transistor, a second transistor, and an active inductor. A gate of the first transistor may receive a first input signal, a gate of the second transistor may receive a second input signal, a source of the second transistor may be coupled to a source of the first transistor, and the active inductor may be coupled to a drain of the first transistor.
    Type: Application
    Filed: November 18, 2004
    Publication date: May 18, 2006
    Inventors: Fabrice Paillet, Tanay Karnik, Jianping Xu
  • CPU power delivery system
    Publication number: 20060099734
    Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
    Type: Application
    Filed: September 30, 2004
    Publication date: May 11, 2006
    Inventors: Siva Narendra, Howard Wilson, Donald Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek De, Shekhar Borkar
  • Regulated sleep transistor apparatus, method, and system
    Patent number: 7042274
    Abstract: A transistor may operate as a sleep transistor or as a regulator.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: May 9, 2006
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Tanay Karnik
  • Method and apparatus for measuring coil current
    Publication number: 20060091896
    Abstract: A method is described that comprises flowing current from one region of a coil to another region of the coil. The flowing induces—through flux linkage—a voltage across a second coil. A second current substantially does not flow through the second coil. The method also includes measuring the current with a first voltage at the another region of the coil and a second voltage at the second coil.
    Type: Application
    Filed: October 29, 2004
    Publication date: May 4, 2006
    Inventors: Gerhard Schrom, Peter Hazucha, Donald Gardner, Vivek De, Tanay Karnik
  • Soft-error rate hardened pulsed latch
    Patent number: 7038515
    Abstract: A latch includes a memory unit, a transfer unit, an inversion unit, and an output unit. The Memory unit includes a number of storage nodes. The transfer unit transfers a data from a data input node to the storage nodes via a plurality of data paths. Each of the data paths includes a pass element controlled by a pulse. The inversion unit inverts the data before the data is transferred from the data input node to at least one of the storage nodes. The output unit outputs the data from the memory unit to a latch output node. The memory unit, the transfer unit, the inversion unit, and the output unit of the latch form a soft-error rate hardened latch structure with a reduced number of elements and reduced power consumption.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: May 2, 2006
    Assignee: Intel Corporation
    Inventors: Stefan Rusu, Peter Hazucha, Tanay Karnik
  • Timing circuit for separate positive and negative edge placement in a switching DC-DC converter
    Patent number: 7030676
    Abstract: A timing circuit independently controls placement of the positive and negative edges of a periodic signal. This signal may then be used to control a wide variety of integrated circuit applications. The timing circuit includes separate programmable delay lines and a signal processor. Each delay line delays an input clock signal by a different increment of time. The signal processor then generates a timing signal from the clock signal, where the timing signal has a first edge controlled by the first delayed clock signal and a second edge controlled by the second delayed clock signal. The edges may be controlled so that the timing signal assumes different logical values for different amounts of time, thereby customizing the signal to any application. An example of one application includes using the timing signal control switching in a DC-DC converter.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: April 18, 2006
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Gerhard Schrom, Tanay Karnik, Vivek De
  • Delay interpolation in a ring oscillator delay stage
    Publication number: 20060071722
    Abstract: According to some embodiments, a circuit includes a delay stage of a ring oscillator. The delay stage may include a first differential pair, a second differential pair, and a third differential pair. The first differential pair may be coupled to a first current-steering circuit, receive a differential input signal, and output a first differential signal. The second differential pair may receive the differential input signal and output a second differential signal, and the third differential pair may be coupled to a second current-steering circuit, receive the second differential signal from the second differential pair, and output the first differential signal. An amount of delay between the differential input signal and the first differential signal is based on relative amounts of current steered by the first current-steering circuit and the second current-steering circuit.
    Type: Application
    Filed: September 29, 2004
    Publication date: April 6, 2006
    Inventors: Fabrice Paillet, David Rennie, Tanay Karnik, Jianping Xu
  • CPU power delivery system
    Publication number: 20060071650
    Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator/converter die bonded to the CPU die in a three dimensional packaging layout.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 6, 2006
    Inventors: Siva Narendra, Howard Wilson, Donald Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek De, Shekhar Borkar