Patents by Inventor Tanay Karnik

Tanay Karnik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Carbon nanotube fuse element
    Publication number: 20090003028
    Abstract: In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programming the memory cell with low current levels.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Ali Keshavarzi, Juanita Kurtin, Janice C. Lee, Vivek De, Tanay Karnik, Timothy L. Deeter
  • DELAY FAULT DETECTION USING LATCH WITH ERROR SAMPLING
    Publication number: 20080307277
    Abstract: Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value.
    Type: Application
    Filed: June 5, 2007
    Publication date: December 11, 2008
    Inventors: James W. Tschanz, Keith A. Bowman, Nam Sung Kim, Chris Wilkerson, Shih-Lien L. Lu, Tanay Karnik
  • CONTROL OF EDDY CURRENTS IN MAGNETIC VIAS FOR INDUCTORS AND TRANSFORMERS IN INTEGRATED CIRCUITS
    Publication number: 20080290980
    Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.
    Type: Application
    Filed: August 6, 2008
    Publication date: November 27, 2008
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Power transformer
    Patent number: 7436277
    Abstract: A multi-phase transformer is provided that includes a first layer having at least a first planar wire and a second planar wire and a second layer formed on the first layer and having at least a third planar wire and a fourth planar wires. At least the first planar wire and the second planar wire of the first layer to form two transformers with at least two planar wires of the second layer. The multi-phase transformer may also include a coupling device to couple one end of the planar wires of the first layer with one of the planar wires of the second layer.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: October 14, 2008
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Gerhard Schrom, Weimin Shi, Edward Burton, Trang Nguyen, Mary Bloechel, legal representative, Tanay Karnik, Bradley Bloechel
  • COMPONENTS WITH ON-DIE MAGNETIC CORES
    Publication number: 20080238602
    Abstract: An apparatus may include a first magnetic layer, a second magnetic layer, and a conductive pattern. The conductive pattern is at a third layer between the first and second magnetic layers. Moreover, one or more magnetic vias connect the first and second magnetic layers. The magnetic layers and vias may operate as ferromagnetic cores or shields. Further they may be integrated on a chip (on-die magnetics). The apparatus may be included in inductors, transformers, transmission lines, and so forth.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: GERHARD SCHROM, DONALD GARDNER, PETER HAZUCHA, FABRICE PAILLET, TANAY KARNIK
  • GROUNDING OF MAGNETIC CORES
    Publication number: 20080238596
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: GERHARD SCHROM, DONALD GARDNER, PETER HAZUCHA, FABRICE PAILLET, TANAY KARNIK
  • Control of eddy currents in magnetic vias for inductors and transformers in integrated circuits
    Patent number: 7423508
    Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Stepwise drivers for DC/DC converters
    Patent number: 7394298
    Abstract: Stepwise drivers for DC/DC converters are described herein. In one embodiment, a stepwise driver is provided to charge or discharge a gate capacitance of a power switch of a DC/DC converter. In a particular embodiment, a stepwise driver example includes multiple switching elements to sequentially switch to charge a gate capacitance of a power switch of a DC/DC converter from a first voltage to a second voltage in multiple steps. Other methods and apparatuses are also described.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: July 1, 2008
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Sung T. Moon, Gerhard Schrom, Tanay Karnik, Vivek De
  • PULSE WIDTH MODULATOR
    Publication number: 20080143408
    Abstract: In accordance with some embodiments, a pulse width modulator having a comparator with an applied adjustable waveform to generate a bit stream with a controllably adjustable duty cycle is provided.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Inventors: Fabrice Paillet, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Sung T. Moon, Donald S. Gardner
  • Signal generating circuit
    Publication number: 20080143407
    Abstract: Embodiments of a signal generating circuit are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Inventors: Gerhard Schrom, Dinesh Somasekhar, Fabrice Paillet, Peter Hazucha, Sung Tae Moon, Tanay Karnik
  • High-speed data sampler for optical interconnect
    Patent number: 7386080
    Abstract: A system and method for sampling a data stream generates a number of clock signals having equally spaced phases and then samples a data stream using the clock signals. The clock phases are preferably based on a predetermined fraction of a data rate frequency of the data stream, and sampling is performed based on predetermined combinations of the clock signals. While the system and method is suitable for sampling data transmitted for a wide variety of data rates, the system and method is especially well-suited to sampling at data transmitted at high rates, for example, equal to or greater than 20 Gb/s.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: June 10, 2008
    Assignee: Intel Corportion
    Inventors: Fabrice Paillet, Tanay Karnik, Jianping Xu
  • Voltage regulation using digital voltage control
    Patent number: 7372382
    Abstract: For one disclosed embodiment, error is sensed in a voltage at an output node. One or more analog signals are generated based on the sensed error. One or more generated analog signals are converted into one or more digital signals. The voltage at the output node is controlled in response to the one or more digital signals.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Saravanan Rajapandian, Gerhard Schrom, Tanay Karnik, Vivek De
  • DUAL RAIL GENERATOR
    Publication number: 20080100371
    Abstract: Some embodiments disclosed herein provide dual rail generators to provide a high and a low supply rail.
    Type: Application
    Filed: October 26, 2006
    Publication date: May 1, 2008
    Inventors: Fabrice Paillet, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Sung T. Moon
  • Programmable high-resolution timing jitter injectors high-resolution timing jitter injectors
    Patent number: 7348821
    Abstract: A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable based on a delay code. Different values of the delay code allow the device to select different delayed signals. The device may select one of the delayed signals from the first circuit for use as a timing signal in a second circuit of the device. The device may also use the delayed signals from the first circuit to evaluate a clock and data recovery circuit. In an embodiment, the circuits may be located on a single die.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Jianping Xu, KyeHyung Lee, Fabrice Paillet, David Rennie, Tanay Karnik
  • Integrated inductors
    Publication number: 20080001698
    Abstract: Multiple-inductor embodiments for use in substrates are provided herein.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 3, 2008
    Inventors: Peter Hazucha, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • Slotted magnetic material for integrated circuit inductors
    Publication number: 20080001699
    Abstract: An embodiment is an inductor that may include a slotted magnetic material to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Magnetic vias for inductors and transformers in integrated circuits
    Publication number: 20080003760
    Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Control of eddy currents in magnetic vias for inductors and transformers in integrated circuits
    Publication number: 20080001701
    Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Laminated magnetic material for inductors in integrated circuits
    Publication number: 20080003699
    Abstract: An embodiment is an inductor that may include a laminated material structure to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electroless plating techniques to form a layer or layers of magnetic material within the laminated material structure, and in particular those magnetic layers adjacent to insulator layers.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Integrated inductor
    Publication number: 20080002380
    Abstract: An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 3, 2008
    Inventors: Peter Hazucha, Edward Burton, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Kaladhar Radhakrishnan, Donald S. Gardner, Sung T. Moon, Tanay Karnik