Abstract: Providing for two-terminal memory cell structures and fabrication that can be achieved with a relatively low temperature process(es) is described herein. By way of example, disclosed two-terminal memory cells can be formed at least in part as a continuous deposition, potentially yielding improved efficiency in manufacturing. Furthermore, various embodiments can be compatible with some existing complementary metal oxide semiconductor fabrication processes, reducing or avoiding retooling overhead that might be associated with modifying existing fabrication processes in favor of other two-terminal memory cell fabrication techniques.

Abstract: Providing for improved programming techniques for endurance and memory retention in two-terminal memory is described herein. In some embodiments, a programming pulse can be configured to provide a minimum pulse time over which a program signal is applied to a two-terminal memory cell, following programming of the two-terminal memory cell. This minimum pulse time can help to stabilize the program state of the two-terminal memory cell, improving stability of the program state (e.g., related to memory retention) and overall increased endurance (e.g., in program cycles) of the two-terminal memory cell. The minimum pulse time can be initiated separately to a programming pulse, or can be integrated as part of the program pulse, in various embodiments. In some embodiments, current compliance or voltage control can be implemented in conjunction with providing programming and minimum pulse time functionality.

Abstract: Providing for a solid state memory cell having a resistive switching memory cell with rectifier characteristics is described herein. By way of example, the solid state memory cell can have one or more layers creating a resistive switching device capable of achieving and maintaining different electrical resistances in response to different voltages applied to the solid state memory cell. Moreover, the solid state memory cell can comprise two or more layers creating a solid state diode device electrically in series with the resistive switching device. The solid state diode device can be configured to permit very low current through the solid state memory cell at voltages less than a breakdown voltage or reverse breakdown voltage. The rectifier characteristics can mitigate sneak path currents in a crossbar memory array, or similar array, facilitating greater sensing margin, reduced likelihood of memory errors, greater die concentration, fast switching times, and other benefits.

Abstract: Providing for preconditioning of multi-programmable, two-terminal memory for improved endurance and switching functionality is described herein. By way of example, one or more pre-conditioning signals can be applied to a memory cell post-fabrication. The preconditioning signal(s) can have relatively small power, avoiding programming of the memory cell, compared with an associated program signal. The preconditioning signal(s) can facilitate reliable erasure of the memory cell following subsequent programming at normal programming power. Accordingly, switching functionality of the two-terminal memory can be preserved, maintaining the multi-programmable nature of the memory cell.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Abstract: A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: A method of programming a non-volatile memory device includes providing a resistive switching device, the resistive switching device being in a first state and characterized by at least a first resistance, applying a first voltage to the resistive switching device in the first state to cause the resistive switching device to change to a second state wherein the second state is characterized by at least a second resistance, wherein the second resistance is greater than the first resistance, and applying a second voltage to the resistive switching device in the second state to cause the resistive switching device to change to a third state, wherein the third state is characterized by at least a third resistance, wherein the second voltage has a magnitude higher than a magnitude of the second voltage, and wherein the third resistance is greater than the second resistance.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Abstract: A method for forming a resistive memory device includes providing a substrate comprising a first metal material, forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the lower region is adjacent to the first metal material, forming an amorphous layer from the upper region of the conductive silicon-bearing layer, and disposing an active metal material above the amorphous layer.

Abstract: Providing for one time programmable, multi-level cell two-terminal memory is described herein. In some embodiments, the one time programmable, multi-level cell memory can have a 1 diode 1 resistor configuration, per memory cell. A memory cell according to one or more disclosed embodiments can be programmed to one of a set of multiple logical bits, and can be configured to mitigate or avoid erasure. Accordingly, the memory cell can be employed as a single program, non-erasable memory. Expressed differently, the memory cell can be referred to as a write once read many (WORM) category of memory.

Abstract: A method for programming a non-volatile memory device includes providing an as-fabricated state-change device having an aluminum doped zinc oxide material first electrode, a p++ polysilicon material second electrode, and a zinc oxide (ZnO) material state-change material there between. A first amplitude bias voltage is applied to the first electrode of the as-fabricated state-change device causing the ZnO material to change form an as-fabricated state to a first state. A second amplitude bias voltage having an opposite polarity having an amplitude similar to the first amplitude is applied to cause the ZnO to change from the first state to a second state substantially similar as the as-fabricated state. A third amplitude bias voltage having a same polarity to the first bias voltage and having an amplitude dissimilar to the first bias voltage is applied to cause the ZnO to change from the second state to a third state.

Abstract: A method for forming a resistive memory device includes providing a substrate comprising a first metal material, forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the lower region is adjacent to the first metal material, forming an amorphous layer from the upper region of the conductive silicon-bearing layer, and disposing an active metal material above the amorphous layer.

Abstract: A non-volatile memory device structure includes a first conductor extending in a first direction, a second conductor extending in a second direction approximately orthogonal to the first direction, an amorphous silicon material disposed in an intersection between the first and second conductors characterized by a first resistance upon application of a first voltage, wherein the first resistance is dependent on a conductor structure comprising material from the second conductor formed in a portion of the resistive switching material, and a layer of material configured in between the second conductor and the amorphous silicon material, wherein the layer maintains at least a portion the conductor structure in the amorphous silicon material, and wherein the layer inhibits conductor species from the portion of the conductor structure from migrating away from the second conductor when a second voltage having an amplitude less than the first voltage is applied.

Abstract: A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, applying a first programming voltage to a shared node of a second electrode of the first resistive element, a first electrode of the second resistive element, and to a gate of a transistor element, and changing a resistance state of the first resistive element to a low resistance state while maintaining a resistance state of the second resistive element, when a voltage difference between the first programming voltage at the second terminal and the first input voltage at the first terminal exceeds a programming voltage associated with the first resistive element.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Abstract: A non-volatile memory device includes a resistive switching device having a first electrode, a second electrode, and a resistive switching element, wherein the resistive switching element comprises a silicon material disposed in an overlapping region between the first electrode and the second electrode, wherein the second electrode comprises at least a metal material physically and electrically in contact with the resistive switching material, wherein the resistive switching element is characterized by a resistance depending on an electric field in the resistive switching element, and a non-linear device coupled between the first electrode and the resistive switching element , wherein the non-linear device is configured to conduct electric current when a voltage greater than a first voltage is applied to the second electrode, wherein the resistive switching device is configured to change from a first state to a second state in response to the first voltage.