Abstract: A method of a read scheme for a non-volatile memory cell. The non-volatile memory cell includes a substrate, a source, a drain and a gate above a channel separated by a nonconducting charge trapping material sandwiched between first and second insulating layers. The method applies a first positive drain-to-source bias, a second positive source-to-substrate bias, and a third positive gate-to-source bias to read the source-side charges trapped in the trapping material near the source side.

Abstract: A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.

Abstract: The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.

Abstract: An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.

Abstract: A trim circuit and method for tuning a current level of a reference cell in a flash memory that includes a sense amplifier to compare a cell current from a memory cell whose gate receives a word line signal voltage with a reference current from the reference cell whose gate receives a bias voltage produced by dividing the word line signal voltage by a voltage divider to thereby produce a sense signal. The voltage divider includes at least a programmable flash cell to serve as a variable resistor whose resistance is determined by programming the programmable flash cell by a programming/erasing circuit in reference to the programming of the memory cell.

Abstract: A method of programming the memory cell comprises setting the memory cell to an initial state of a first gate threshold voltage, performing a processing sequence including: applying a voltage bias between the gate and the first junction region to cause electric hole to migrate towards and be retained in the trapping layer, and evaluating a read current generated in response to the voltage bias to determine whether a second gate threshold voltage is reached, wherein the second gate threshold voltage is lower than the first gate threshold voltage. The processing sequence is repeated a number of times by varying one or more time the voltage bias between the gate and the first junction region until the second gate threshold voltage is reached and the memory cell is in a program state.

Abstract: A method of narrowing the threshold voltage distribution in a memory. The method includes separating the erase and erase identification of odd memory cells from the erase and erase identification of even memory cells in an advanced non-volatile memory so that the distribution of the threshold voltage is narrowed.

Abstract: One embodiment of the present invention provides a system having a nonvolatile memory comprising a p type semiconductor substrate, an oxide layer over the p type semiconductor substrate, a nitride layer over the oxide layer, an additional oxide layer over the nitride layer, a gate over the additional oxide layer, two N+ junctions in the p type semiconductor layer, a source and drain respectively formed in the two N+ junctions, a first bit and a second bit in the nonvolatile memory, and accordingly at least two states of operation (i.e., erase and program) therefor. That is, one bit in the nonvolatile memory can either be in an erase state or program state. For erasing a bit, electrons are injected at the gate of the nonvolatile memory. For programming a bit, electric holes are injected or electrons are reduced for that bit.

Abstract: The invention advantageously provides a device and method for optimal data retention in a trapping nonvolatile memory cell. A preferred embodiment of the invention provides a trapping nonvolatile memory cell comprising a semiconductor substrate further comprising a source, a drain spaced from the source, and a channel region formed between the source and the drain, a first isolating layer overlying the channel region, a nonconducting charge trapping layer overlying the first isolating layer and trapping electrical charges therein using charge injection, a second isolating layer overlying the trapping layer, and a gate overlying the second isolating layer. After the charges are trapped in the trapping layer, some of the trapped charges are detrapped using electrical field enhanced electron detrapping technique. The charges in the trapping layer are repeatedly trapped and detrapped shallow traps until a desired number of the deep traps are stored in the trapping layer.

Abstract: A non-volatile memory device is described, comprising a plurality of memory cells, a plurality of word lines, a plurality of drain lines, and a plurality of source lines, wherein two adjacent memory cells in a column constitute a cell pair, and all cell pairs are arranged in rows and columns. The two memory cells in each cell pair share a source region, and two adjacent cell pairs in a column share a drain region. The source regions and the gates of the memory cells in the same row are coupled to a source line and a word line, respectively, and the drain regions of the memory cells in the same column are coupled to a drain line.

Abstract: A MOSFET structure comprises a tortuous gate having a first sidewall and a second sidewall, disposed over a semiconductor substrate. A source region is disposed within the semiconductor substrate adjacent to the first sidewall of the tortuous gate. The source region comprises a broader part and a narrower part. Contacts are positioned above the broader part of the source region and are in contact with the broader part of the source region. A drain region is disposed within the semiconductor substrate adjacent to the second sidewall of the tortuous gate. The drain region comprises a broader part and a narrower part. Contacts are disposed above the broader part of the drain region and are in contact with the broader part of the drain region. The broader part of the drain region is disposed opposite to the narrower part of the source region. The narrower part of the drain region is disposed opposite to the broader part of the source region.

Abstract: An erasing method for a p-channel nitride read only memory. The method is used for a p-channel nitride read only memory having charges stored in a charge-trapping layer. A positive voltage is applied to the control gate and a negative voltage to the drain; also, the source is floating and the n-well is grounded. The voltage difference between the positive voltage applied to the control gate and the negative voltage to the drain is sufficient to trigger a band-to-band induced hot electron injection to erase the p-channel nitride read only memory.

Abstract: The invention provides a dual-use infrared thermometer, including a main body and a probe, wherein the probe is formed at the top end of the main body; a hollow sleeve, whose shape is corresponding to the probe to be sleeved onto the probe for forming a forehead-type probe; and a temperature detection device, provided inside the main body to sense the infrared emissions and then convert the emissions into electronic signal, while a build-in temperature calibration procedure is employed to calculate the measured temperature. Alternatively,an interface switch device is provided on the surface of the probe, extending to the internal of the main body to be electrically connected to the temperature detection device. Thus, by detecting whether the hollow sleeve has been sleeved on the probe, the temperature detection device will be activated to switch to either the ear temperature calibration procedure or the forehead temperature calibration procedure.

Abstract: An electrostatic discharge (ESD) device used with a high-voltage input pad is described. The ESD device serves as a secondary device of a two-stage protection circuit, and comprises a substrate, a first MOS transistor and a second MOS transistor. The first MOS transistor is disposed on the substrate and comprises a first gate, a first drain and a first source, wherein the first gate is coupled to a bias Vg1, and the first drain is coupled to the high-voltage input pad. The second MOS transistor is disposed on the substrate and comprises a second gate, a second drain and a second source, wherein the second gate and the second source are both grounded, and the second drain is electrically connected with the first source of the first MOS transistor.

Abstract: The invention advantageously provides a nonvolatile memory device and associated methods therefore, and, more particularly, an optimally designed nonvolatile memory device and methods therefor that advantageously prevent data loss in its trapping layer. A preferred embodiment of the method for operating a nonvolatile memory cell according to the invention advantageously comprises the steps of programming the memory cell, injecting electrons into a trapping layer of the memory cell from a semiconductor substrate, erasing the memory cell, detrapping the memory cell, and repeating the erasing and detrapping steps until a threshold voltage of the memory cell reaches a predetermined value. For the detrapping step, electrons can be detrapped from the trapping layer to a channel region of the memory cell, or to a gate of the memory cell.

Abstract: A method for operating a P-channel SONOS memory device that has a charge trapping layer located on a substrate, a gate electrode located on the trapping layer, two doped regions located in the substrate at each side of the charge trapping layer. The two doped regions are set to be a drain region and a source region. When a programming action is intended, the gate electrode and the drain region are applied with a first negative high-level bias, and the source region and the substrate are applied with a grounded voltage. When an erasing action is intended, the gate electrode is a second negative bias which is smaller than the first negative voltage in absolute value. In the mean time, the drain region is applied with the third negative bias and the substrate is applied with a grounded voltage. The third negative voltage is larger than the second negative bias in absolute value.

Abstract: The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.

Abstract: A mask ROM device is described. The mask ROM device includes a substrate, a gate, a double diffused source/drain region that comprises a first doped region and a second doped region, a channel region, a coding region, a dielectric layer and a word line. The gate is disposed on the substrate. The double diffused source/drain region is positioned beside the sides of the gate in the substrate, wherein the second doped region is located at the periphery of the first doped region in the substrate. The channel region is located between the double diffused source/drain region in the substrate. The coding region is disposed in the substrate at the intersection between the sides of the channel region and the double diffused source/drain region. The dielectric layer is disposed above the double diffused source/drain region, while the word line is disposed above the dielectric layer and the gate.

Abstract: A fabrication method for a flash memory device with a split floating gate is described. The method provides a substrate, wherein an oxide layer and a patterned sacrificial layer are sequentially formed on the substrate. Ion implantation is then conducted to form source/drain regions with lightly doped source/drain regions in the substrate beside the sides of the patterned sacrificial layer using the patterned sacrificial layer as a mask. Isotropic etching is further conducted to remove a part of the patterned sacrificial layer, followed by forming two conductive spacers on the sidewalls of the patterned sacrificial layer. The patterned sacrificial layer and oxide layer that is exposed by the two conductive spacers are then removed to form two floating gates. Subsequently, a dielectric layer and a control gate are formed on the substrate.

Abstract: An ESD protection apparatus for a high-voltage input pad comprises a modulator connected between the input pad and a snapback device with first and second guard rings surrounding the modulator, third guard ring surrounding the snapback device, and first and second guard ring control circuits to control the guard rings such that the protection apparatus has higher triggering and holding voltages under normal operation and lower triggering and holding voltages under ESD event.