Patents by Inventor Tao-Cheng Lu

Tao-Cheng Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for fabricating a non-volatile memory
    Patent number: 6706575
    Abstract: A method for fabricating a non-volatile memory is described. A substrate having a strip stacked structure thereon is provided. A buried drain is then formed in the substrate beside the strip stacked structure and an insulating layer is formed on the buried drain. A silicon layer and a cap layer are sequentially formed over the substrate. The cap layer, the silicon layer and the strip stacked structure are then patterned successively in a direction perpendicular to the buried drain, wherein the strip stacked structure is patterned into a plurality of gates. A liner oxide layer is formed on the exposed surfaces of the gates, the substrate and the silicon layer. Thereafter, the cap layer is removed and a metal salicide layer is formed on the exposed surface of the silicon layer.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: March 16, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Tso-Hung Fan, Yen-Hung Yeh, Kwang-Yang Chan, Mu-Yi Liu, Tao-Cheng Lu
  • Erasing method for non-volatile memory
    Publication number: 20040047186
    Abstract: An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.
    Type: Application
    Filed: November 6, 2002
    Publication date: March 11, 2004
    Inventors: Wen-Jer Tsai, Chih-Chieh Yeh, Tao-Cheng Lu, Samuel C. Pan
  • ESD protection apparatus and method for dual-polarity input pad
    Publication number: 20040027744
    Abstract: An ESD protection apparatus for dual-polarity input pad comprises a triple-well formed with a first, second and third regions to form an SCR structure. A first and second ground connection regions of opposite conductivity types are formed on the first region, a first and second input connection regions of opposite conductivity types are formed in the third region, and a bridge region is formed across the second region and extends to the first and third regions. Under normal operation, the first, second, and third regions form two back-to-back diodes. Under positive polarity ESD event, breakdown is occurred between the bridge and first regions to thereby trigger an SCR circuit for positive polarity ESD protection. Under negative polarity ESD event, breakdown is occurred between the bridge and third regions to thereby trigger an SCR circuit for negative polarity ESD protection.
    Type: Application
    Filed: June 27, 2003
    Publication date: February 12, 2004
    Inventors: Meng-Huang Liu, Chun-Hsiang Lai, Shin Su, Tao-Cheng Lu
  • Nonvolatile semiconductor memory cell with electron-trapping erase state and methods for operating the same
    Patent number: 6690601
    Abstract: A preferred embodiment of the invention provides a trapping nonvolatile memory cell comprising a P type semiconductor substrate with a N+ source and a N+ drain being formed on the semiconductor substrate, a channel being formed between the source and the drain. A first isolating layer, a nonconducting charge trapping layer, a second isolating layer and a gate are sequentially formed above the channel. The trapping layer stores an amount of electrons as the nonvolatile memory cell is erased.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: February 10, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Chieh Yeh, Wen-Jer Tsai, Tao-Cheng Lu
  • Reference current generation circuit for multiple bit flash memory
    Patent number: 6687160
    Abstract: A reference current generation circuit for the multiple bit flash memory provided by the present invention applies the same boosted word-line voltage to the gates of different reference current generation unit's reference cells, and uses different gate lengths from different reference cells to obtain the reference currents with different levels that are needed. Therefore, it effectively solves the problem of the reference currents having different drifts along with the variance of the temperature and the power voltage Vcc.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: February 3, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Tso-Hung Fan, Chih-Chieh Yeh, Tao-Cheng Lu
  • Semiconductor device structure
    Patent number: 6683352
    Abstract: A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate and the semiconductor substrate. A drain region is disposed within the semiconductor substrate, wherein the drain region is surrounded by the p-shape gate. A source region is disposed within the semiconductor substrate, wherein the source region surrounds the p-shape gate. A silicide structure is disposed on the source/drain regions and the p-shape gate.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: January 27, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Tsung-Hsuan Hsieh, Yao-Wen Chang, Tao-Cheng Lu
  • Erasing method for p-channel NROM
    Patent number: 6671209
    Abstract: An erasing method for a p-channel nitride read only memory. The method is used for a p-channel nitride read only memory having charges stored in a charge-trapping layer. A positive voltage is applied to the control gate and a negative voltage to the drain; also, the source is floating and the n-well is grounded. The voltage difference between the positive voltage applied to the control gate and the negative voltage to the drain is sufficient to trigger a band-to-band induced hot electron injection to erase the p-channel nitride read only memory.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: December 30, 2003
    Assignee: Macronix International Co., Ltd.
    Inventors: Hung-Sui Lin, Han-Chao Lai, Tao-Cheng Lu
  • Electrostatic discharge protection device
    Publication number: 20030234426
    Abstract: An ESD protection device. The ESD protection device is set between a memory device, a second voltage level and a pad coupled to a first voltage level. The ESD protection device includes a first second type doped region formed on the first type substrate and coupled to the first voltage level, a second second type doped region formed on the first type substrate and coupled to the second voltage level, a third second type doped region formed on the first type substrate, a second type well formed between the first second type doped region and the third second type doped region, and an isolation element formed between the second second type doped region and the third second type doped region.
    Type: Application
    Filed: October 21, 2002
    Publication date: December 25, 2003
    Inventors: Meng-Huang Liu, Chun-Hsiang Lai, Shin Su, Tao-Cheng Lu
  • Gate-equivalent-potential circuit and method for I/O ESD protection
    Publication number: 20030235022
    Abstract: A gate-equivalent-potential circuit and method for an I/O pad ESD protection arrangement including used and unused MOS fingers connected to the I/O pad comprises a switch connected between the gates of the MOS fingers, an ESD detector connected to the switch to turn on the switch upon an ESD event and a gate-modulated circuit connected to the gate of the unused finger to couple a voltage thereto to reduce the triggering voltage of the transistors within the fingers.
    Type: Application
    Filed: October 9, 2002
    Publication date: December 25, 2003
    Inventors: Chun-Hsiang Lai, Meng-Huang Liu, Shin Su, Tao-Cheng Lu
  • Silicon controlled rectifier structure with guard ring controlled circuit
    Publication number: 20030234405
    Abstract: The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.
    Type: Application
    Filed: June 25, 2002
    Publication date: December 25, 2003
    Applicant: Macronix International Co., Ltd.
    Inventors: Chen-Shang Lai, Meng-Huang Liu, Shin Su, Tao-Cheng Lu
  • Reference current generating circuit of multiple bit flash memory
    Patent number: 6665212
    Abstract: The reference current generation circuit of a multiple bit flash memory. An identical boosted word-line voltage is applied to the gate terminal of reference memory cells in different reference current generation units and a different substrate voltage is applied to the substrate of each reference memory cell so that different reference currents are produced. This arrangement reduces different degree of shifting in the reference currents due to temperature and source voltage Vcc variation.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: December 16, 2003
    Assignee: Macronix International Co., Ltd.
    Inventors: Tso-Hung Fan, Chih-Chieh Yeh, Tao-Cheng Lu
  • Substrate pump circuit and method for I/O ESD protection
    Patent number: 6661273
    Abstract: A substrate pump circuit and method for I/O ESD protection including NMOS fingers connected to the interconnection between an I/O pad and an internal circuit comprises a MOS device connected to the interconnection between the I/O pad and the internal circuit and the substrate under the control of a switch to turn it on to conduct a pumping current through the substrate resistor when the I/O pad is under ESD stress, so as to pull up the potential of the substrate adjacent to the NMOS fingers, resulting in the reduction of the triggering voltage of the NMOS fingers.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: December 9, 2003
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiang Lai, Meng-Huang Liu, Shin Su, Tao-Cheng Lu
  • Apparatus and method for programming virtual ground nonvolatile memory cell array without disturbing adjacent cells
    Patent number: 6657894
    Abstract: A virtual ground nonvolatile memory cell array is formed by a plurality of adjacent nonvolatile memory cells arranged in rows and columns so as to form an array. Each of the nonvolatile memory cells is formed by an N channel MOSFET with a trapping layer formed between two isolating layers. In the erase state, the trapping layer stores an amount of electrons. A method for programming the virtual ground nonvolatile memory cell array is also disclosed. The potentials applied to the bitlines and wordlines in the array are preset to program nonvolatile memory cells and not to disturb cells adjacent to the nonvolatile memory cell to be programmed.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: December 2, 2003
    Assignee: Macronix International Co., Ltd,
    Inventors: Chih-Chieh Yeh, Wen-Jer Tsai, Tao-Cheng Lu
  • Fabrication method for mask read only memory device
    Publication number: 20030219930
    Abstract: A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.
    Type: Application
    Filed: May 24, 2002
    Publication date: November 27, 2003
    Inventors: Tso-Hung Fan, Yen-Hung Yeh, Kwang-Yang Chan, Mu-Yi Liu, Tao-Cheng Lu
  • Nitride read-only memory cell for improving second-bit effect and method for making thereof
    Patent number: 6649971
    Abstract: A NROM cell for reducing for reducing the second-bit effect is described. The NORM cell of the present invention is formed with a substrate, a silicon oxide/silicon nitride/silicon oxide (ONO) layer disposed on the substrate, a gate disposed on the silicon oxide/silicon nitride/silicon oxide layer, source/drain regions configured in the substrate beside the gate, and a shallow pocket doped region configured between the source/drain regions and the ONO layer beside the gate. The depth of the shallow pocket doped region is sufficiently small to prevent interference to the current flow that travels to the source/drain regions.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: November 18, 2003
    Assignee: Macronix International Co., Ltd.
    Inventors: Yen-Hung Yeh, Wen-Jer Tsai, Mu-Yi Liu, Kwang-Yang Chan, Tso-Hung Fan, Tao-Cheng Lu
  • Non-volatile memory and operating method thereof
    Patent number: 6646924
    Abstract: A non-volatile memory is described, which comprises a plurality of memory cells, a plurality of word lines, a plurality of drain lines and a plurality of source lines. Two adjacent memory cells in the same row share a source and are grouped into a cell pair, and all of the cell pairs are arranged in rows and columns, wherein two cell pairs in the same row share a drain. The sources of the memory cells in the same row are connected to a source line, and the drains of the memory cells in the same row are connected to a drain line. The gates of the memory cells in the same column are coupled to a word line.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: November 11, 2003
    Assignee: Macronix International Co, Ltd.
    Inventors: Wen-Jer Tsai, Chih-Chieh Yeh, Tao-Cheng Lu
  • Mask read only memory device and fabrication method thereof
    Publication number: 20030205770
    Abstract: A mask ROM and a fabrication method thereof are described. The method includes forming a buried drain region in the substrate and forming a gate oxide layer on the substrate. A patterned dual-layer structure dielectric layer is formed on the gate oxide layer. A conductive layer, which is perpendicular to the direction of the buried drain region, is then formed on the gate oxide layer and on the dual-layer structure dielectric layer to form a plurality of code memory cells. The code memory cells that comprise the dual-layer structure dielectric layer correspond to the logic state of “0”, while the memory cells that do not comprise the dual-layer structure dielectric layer correspond to the logic state of “1”.
    Type: Application
    Filed: June 7, 2002
    Publication date: November 6, 2003
    Inventors: Yao-Wen Chang, Tao-Cheng Lu
  • Structure of two-bit mask read-only memory device and fabricating method thereof
    Publication number: 20030205764
    Abstract: A structure of a 2-bit mask ROM device and a fabrication method thereof are provided. The memory structure includes a substrate, a gate structure, a 2-bit coding implantation region, a spacer, a buried drain region, an isolation structure and a word line. The gate structure is disposed on the substrate, while the coding implantation region is located in the substrate under the side of the gate structure. Further, at least one spacer is arranged beside the side of the gate structure and a buried drain region is disposed in the substrate beside the side of the spacer. Moreover, the buried drain region and the coding implantation region further comprise a buffer region in between. Additionally, an insulation structure is arranged on the substrate that is above the buried drain region, while the word lien is disposed on the gate structure.
    Type: Application
    Filed: May 8, 2002
    Publication date: November 6, 2003
    Inventors: Mu-Yi Liu, Kwang-Yang Chan, Yen-Hung Yeh, Tso-Hung Fan, Tao-Cheng Lu
  • Reference current generation circuit for multiple bit flash memory
    Patent number: 6643176
    Abstract: A reference current generation circuit for the multiple bit flash memory provided by the present invention applies the same boosted word-line voltage to a voltage dividing circuit of the different reference current generation unit, so as to generate a gate voltage for the different reference current generation unit's reference cell to obtain the reference currents with different levels that are needed. Therefore, it effectively solves the problem of the reference currents having different drifts along with the variance of the temperature and the power voltage Vcc.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: November 4, 2003
    Assignee: Macronix International Co., Ltd.
    Inventors: Tso-Hung Fan, Chih-Chieh Yeh, Tao-Cheng Lu
  • Structure of a mask ROM device
    Publication number: 20030201501
    Abstract: A mask ROM device is described. The mask ROM device includes a substrate, a gate, a double diffused source/drain region that comprises a first doped region and a second doped region, a channel region, a coding region, a dielectric layer and a word line. The gate is disposed on the substrate. The double diffused source/drain region is positioned beside the sides of the gate in the substrate, wherein the second doped region is located at the periphery of the first doped region in the substrate. The channel region is located between the double diffused source/drain region in the substrate. The coding region is disposed in the substrate at the intersection between the sides of the channel region and the double diffused source/drain region. The dielectric layer is disposed above the double diffused source/drain region, while the word line is disposed above the dielectric layer and the gate.
    Type: Application
    Filed: May 24, 2002
    Publication date: October 30, 2003
    Inventors: Tso-Hung Fan, Mu-Yi Liu, Kwang-Yang Chan, Yen-Hung Yeh, Tao-Cheng Lu