Patents by Inventor Tao Cheng

Tao Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180114779
    Abstract: A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.
    Type: Application
    Filed: December 20, 2017
    Publication date: April 26, 2018
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng
  • Patent number: 9908203
    Abstract: A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: March 6, 2018
    Assignee: MEDIATEK INC.
    Inventors: Tao Cheng, Wen-Sung Hsu, Shih-Chin Lin
  • Patent number: 9905515
    Abstract: The present invention provides an integrated circuit (IC) package with stress releasing structure. The IC package comprises: a metal plane, a substrate, an IC chip, and an IC fill layer. The metal plane has at least one first etching line for separating the metal plane into a plurality of areas. The substrate is formed on metal layer. The IC chip is formed on the substrate, and the IC fill layer is formed around the IC chip. The at least one first etching line forms at least one half cut line in the metal plane and the substrate.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: February 27, 2018
    Assignee: MediaTek Inc.
    Inventors: Chin-Chiang Chang, Tao Cheng
  • Patent number: 9881902
    Abstract: A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: January 30, 2018
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng
  • Publication number: 20170338183
    Abstract: A manufacturing method of a semiconductor package includes the follow steps. Firstly, a carrier is provided. Then, a package substrate is formed. Then, a first electronic component is disposed above the second conductive layer of the package substrate. Then, a second package body encapsulating the first electronic component and the second conductive layer is formed. Then, the carrier is carried. Wherein in the step of forming the package substrate includes a step of forming a first conductive layer on the carrier, a step of forming a first pillar layer on the first conductive layer, a step of forming a first package body encapsulating the first conductive layer and the first pillar layer and a step of forming a second conductive layer on the first pillar layer.
    Type: Application
    Filed: August 9, 2017
    Publication date: November 23, 2017
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng, Andrew C. Chang
  • Patent number: 9779880
    Abstract: The present invention provides a resin composition comprising: 1 to 20 parts by weight of a reinforcing fiber; 0.2 to 5 parts by weight of an anti-settling agent; 20 to 40 parts by weight of an epoxy resin; 0.1 to 3 parts by weight of a curing agent; and 50 to 75 parts by weight of a high dielectric constant filler. The present invention further provides a dielectric layer produced from the resin composition and a capacitor comprising the dielectric layer. In the dielectric layer made from the resin composition provided by the present invention, the fibers can be evenly dispersed and can enhance the mechanical strength of the resin composition, and cooperate with the epoxy resin to bring excellent toughness. Therefore, the mechanical strength of the produced dielectric layer can be remarkably improved, and its fragility can be effectively overcome when the dielectric layer is used in the PCB double-side etching process.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 3, 2017
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Tao Cheng, Qilin Chen, Zhou Jin
  • Patent number: 9774615
    Abstract: Techniques for detecting anomalous network traffic are disclosed. In one particular embodiment, the techniques may be realized as a method for detecting anomalous network traffic comprising the steps of receiving a list including a plurality of processes and, for each process, a list of approved types of network traffic; monitoring network traffic of each process on the list of processes; upon detecting network traffic for a process on the list of processes, determining that the type of network traffic detected is not on the list of approved types for that process; and identifying the process as infected based on determining that the type of network traffic detected is not on the list of approved types for that process.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: September 26, 2017
    Assignee: Symantec Corporation
    Inventors: Kevin Alejandro Roundy, Jie Fu, Tao Cheng, Zhi Kai Li, Fanglu Guo, Sandeep Bhatkar
  • Publication number: 20170263559
    Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Applicant: MediaTek Inc.
    Inventors: Ching-Chung Ko, Tao Cheng, Tien-Yueh Liu, Ta-Hsi Chou, Peng-Cheng Kao, Ling-Wei Ke
  • Patent number: 9761534
    Abstract: A semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive layer, a first pillar layer, a first package body and a second conductive layer, wherein the first pillar layer is formed on the first conductive layer, the first package body encapsulates the first conductive layer and the first pillar layer, and the second conductive layer electrically connects to the first pillar layer. The first electronic component is disposed above the second conductive layer of the package substrate. The second package body encapsulates the first electronic component and the second conductive layer.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: September 12, 2017
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng, Andrew C. Chang
  • Patent number: 9698102
    Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 4, 2017
    Assignee: MediaTek Inc.
    Inventors: Ching-Chung Ko, Tao Cheng, Tien-Yueh Liu, Ta-Hsi Chou, Peng-Cheng Kao, Ling-Wei Ke
  • Publication number: 20170154137
    Abstract: A device may detect a user interaction, via a user interface, with a particular component of a model. The device may generate a set of components, associated with the particular component, based on detecting the user interaction with the particular component of the model. The device may cause a representation of the set of components to be provided, via the user interface, in association with the model. The representation may indicate that the set of components are associated with permitting interoperability.
    Type: Application
    Filed: October 19, 2016
    Publication date: June 1, 2017
    Inventors: Mojdeh SHAKERI, Tao Cheng, Robert O. Aberg, Michael D. Tocci, Jamieson M. Cobleigh, Haihua Feng, Kaushik Krishnasamy
  • Publication number: 20170136582
    Abstract: A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.
    Type: Application
    Filed: January 31, 2017
    Publication date: May 18, 2017
    Inventors: Tao Cheng, Wen-Sung Hsu, Shih-Chin Lin
  • Publication number: 20170129767
    Abstract: The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.
    Type: Application
    Filed: January 20, 2017
    Publication date: May 11, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Tsai-Hao HUNG, Shih-Chi KUO, Tsung-Hsien LEE, Tao-Cheng LIU
  • Patent number: 9625520
    Abstract: Latch-up test device and method are provided, and the method includes following steps. A set operation is performed for setting a basic test value according to a test range and setting a trigger pulse and a predetermined error value by the basic test value. A test on a test chip in a wafer under test is performed by the trigger pulse, and whether the test chip is in a latch-up state is determined. Whether to update a test range and a latch-up threshold value and whether to return to the step of performing the set operation are determined according to a determination result, the latch-up threshold value and the basic test value. When the test chip is in the latch-up state and a difference between the latch-up threshold value and the basic test value is not greater than the predetermined error value, the test on the test chip is stopped.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: April 18, 2017
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Shih-Yu Wang, Yao-Wen Chang, Tao-Cheng Lu
  • Publication number: 20170084541
    Abstract: A semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive layer, a first pillar layer, a first package body and a second conductive layer, wherein the first pillar layer is formed on the first conductive layer, the first package body encapsulates the first conductive layer and the first pillar layer, and the second conductive layer electrically connects to the first pillar layer. The first electronic component is disposed above the second conductive layer of the package substrate. The second package body encapsulates the first electronic component and the second conductive layer.
    Type: Application
    Filed: May 24, 2016
    Publication date: March 23, 2017
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng, Andrew C. Chang
  • Patent number: 9597752
    Abstract: A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: March 21, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tao Cheng, Wen-Sung Hsu, Shih-Chin Lin
  • Patent number: 9594831
    Abstract: A targeted disambiguation system is described herein which determines true mentions of a list of named entities in a collection of documents. The list of named entities is homogenous in the sense that the entities pertain to the same subject matter domain. The system determines the true mentions by leveraging the homogeneity in the list, and, more specifically by applying a context similarity hypothesis, a co-mention hypothesis, and an interdependency hypothesis. In one implementation, the system executes its analysis using a graph-based model. The system can operate without the existence of additional information regarding the entities in the list; nevertheless, if such information is available, the system can integrate it into its analysis.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: March 14, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chi Wang, Kaushik Chakrabarti, Tao Cheng, Surajit Chaudhuri
  • Patent number: 9574878
    Abstract: A terminal device is described that includes a housing configured to accommodate various components of the terminal device; a first sensing unit configured to collect first status information of the terminal device; a second sensing unit configured to collect second status information of the terminal device; and a processing unit configured to determine a manner that a user holds the terminal device based on the first status information and the second status information.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: February 21, 2017
    Assignee: LENOVO (BEIJING) CO., LTD.
    Inventors: Qian Zhao, Hanfeng Zheng, Hao Chen, Yufei Zhang, Chenghu Wu, Tao Cheng, Xiaofei Xu, Xiaoming Liu
  • Publication number: 20170040292
    Abstract: A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.
    Type: Application
    Filed: May 24, 2016
    Publication date: February 9, 2017
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng
  • Publication number: 20170031579
    Abstract: According to the present invention, a terminal executes a program correlated to content displayed in a window, etc., of a browser operating in the terminal. When the content is loaded into the window, etc., by execution of the program, the terminal registers a callback function by a window.requestAnimationFrame method assigned to the window, etc. When the callback function is invoked, the terminal determines, on the basis of an interval of timestamps at which the callback function is invoked with respect to the window, etc., whether or not the window, etc., is being browsed by a user, and re-registers the callback function by the window.requestAnimationFrame method assigned to the window, etc.. The terminal intermittently notifies a server of the result of the determination.
    Type: Application
    Filed: February 27, 2015
    Publication date: February 2, 2017
    Inventors: Tao CHENG, Martin MIRANDA