Patents by Inventor Tao Cheng

Tao Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10641958
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao-Cheng Liu, Tsai-Hao Hung, Shih-Chi Kuo
  • Publication number: 20200080138
    Abstract: The present invention relates to the field of noninvasive prenatal gene testing by high-through sequencing technologies. Particularly, the present application relates to a method for determining the content of cell-free fetal DNA in maternal peripheral blood.
    Type: Application
    Filed: March 15, 2017
    Publication date: March 12, 2020
    Applicant: BERRY GENOMICS CO., LTD
    Inventors: Xiaojie ZHANG, Tao CHENG, Xiangbin CHEN, Jianguang ZHANG
  • Publication number: 20200081329
    Abstract: A projector system includes a connector attachable to a lighting wiring base mounted on a ceiling surface of a room, a housing hanging from the connector, a communicator accommodated in the housing to obtain content to be projected onto a wall surface of the room, a projection unit accommodated in the housing to emit emission light to project a picture including the content onto the wall surface, a brightness sensor to sense a brightness of the room, and a corrector to control the emission light to correct an effect of a state of the wall surface on the projected picture in accordance with the brightness of the room.
    Type: Application
    Filed: September 20, 2018
    Publication date: March 12, 2020
    Inventor: Tao Cheng
  • Patent number: 10508020
    Abstract: The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsai-Hao Hung, Shih-Chi Kuo, Tsung-Hsien Lee, Tao-Cheng Liu
  • Publication number: 20190376671
    Abstract: A ceiling-mounted device support includes an engagement portion to be engaged with an attachment portion of a ceiling-mounted device mounted on a ceiling surface of a room with an adapter, and includes a side wall having an open upper end, an open lower end, and an internal space, and a support portion having two ends connected to the side wall and extending through the space. The engagement portion is to be engaged with the attachment portion, and the support portion is supportable with a palm and grippable with digits of a hand.
    Type: Application
    Filed: July 17, 2019
    Publication date: December 12, 2019
    Inventor: Tao Cheng
  • Publication number: 20190370420
    Abstract: Systems and methods automatically construct a realization of a model from an available set of alternative co-simulation components, where the realization meets one or more objectives, such as fidelity, execution speed, or memory usage, among others. The systems and methods may construct the realization model by setting up and solving a constrained optimization problem, which may select particular ones of the alternative co-simulation components to meet the objectives. The systems and methods may configure the realization, and execute the realized model through co-simulation. The systems and methods may employ and manage different execution engines and/or different solvers to run the realization of the model.
    Type: Application
    Filed: May 6, 2019
    Publication date: December 5, 2019
    Inventors: Haihua Feng, Tao Cheng, John E. Ciolfi, Pieter J. Mosterman, Fu Zhang
  • Patent number: 10456405
    Abstract: Provided are a compound of the formula below, and a pharmaceutically acceptable salt or stereoisomer thereof that can be used for treating cardiovascular diseases and compositions containing the compounds. The compounds, a pharmaceutically acceptable salt or stereoisomer thereof and the compositions can improve lipid metabolism disorders by increasing high-density lipoprotein cholesterol in blood; in addition, the compounds, a pharmaceutically acceptable salt or stereoisomer thereof and the compositions can also release nitric oxide, and reduce the onset risk of cardiovascular diseases by means of relaxing blood vessels, lowering blood pressure, inhibiting platelet adhesion and aggregation and maintaining vascular tension, and thus play an important role in preventing and treating the occurrence and development of cardiovascular diseases.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: October 29, 2019
    Assignees: ZHEJIANG HUAHAI PHARMACEUTICAL CO., LTD, SHANGHAI SYNERGY PHARMACEUTICAL SCIENCES CO., LTD
    Inventors: Jian Ge, Yunfei Li, Zhen Zhang, Yijin Wang, Jiamiao Wang, Tao Cheng
  • Publication number: 20190293867
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Application
    Filed: April 8, 2019
    Publication date: September 26, 2019
    Inventors: Tao-Cheng LIU, Tsai-Hao Hung, Shih-Chi Kuo
  • Patent number: 10409469
    Abstract: According to the present invention, a terminal executes a program correlated to content displayed in a window, etc., of a browser operating in the terminal. When the content is loaded into the window, etc., by execution of the program, the terminal registers a callback function by a window.requestAnimationFrame method assigned to the window, etc. When the callback function is invoked, the terminal determines, on the basis of an interval of timestamps at which the callback function is invoked with respect to the window, etc., whether or not the window, etc., is being browsed by a user, and re-registers the callback function by the window.requestAnimationFrame method assigned to the window, etc. The terminal intermittently notifies a server of the result of the determination.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: September 10, 2019
    Assignee: POPIN INC.
    Inventors: Tao Cheng, Martin Miranda
  • Publication number: 20190225989
    Abstract: A gene knockin method and a kit for gene knockin are provided.
    Type: Application
    Filed: January 19, 2018
    Publication date: July 25, 2019
    Applicant: Institute of Hematology and Blood Disease Hospital, CAMS & PUMC
    Inventors: Tao CHENG, Jianping ZHANG, Xiaolan LI, Xiao-Bing ZHANG
  • Patent number: 10354974
    Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a first package which includes at least a semiconductor die, a dielectric structure surrounding the semiconductor die, and a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die. The package structure also includes an interposer substrate over the first package and a plurality of conductive features in or over the interposer substrate. The package structure further includes a second package over the interposer substrate, and the first package electrically couples the second package through the conductive structures and the conductive features.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: July 16, 2019
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Andrew C. Chang, Tao Cheng
  • Patent number: 10312222
    Abstract: A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 4, 2019
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng
  • Patent number: 10274678
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao-Cheng Liu, Tsai-Hao Hung, Shih-Chi Kuo
  • Publication number: 20190123579
    Abstract: The invention provides a battery powered device, which comprises a battery pack, at least one switch, a power management chip, and a pre-powered circuit. The pre-powered circuit comprises a buck and current-limiting module. The buck and current-limiting module comprises at least one zener diode and at least one current-limiting resistor. When the switch is turned off, the battery pack will be powered to a system device by the pre-powered circuit. Thus, the battery pack can be powered to the system device by the pre-powered circuit even if the battery powered device is operated in a standby mode. Besides, the power management chip can be operated in the standby state when the battery powered device is powered by the pre-powered circuit, so as to reduce the consumption of the battery energy and therefore extend the powered time of the battery powered device.
    Type: Application
    Filed: March 19, 2018
    Publication date: April 25, 2019
    Inventors: Chia-Chang CHEN, Tao-Cheng WU
  • Publication number: 20190051609
    Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 14, 2019
    Inventors: Wen-Sung HSU, Tao CHENG, Nan-Cheng CHEN, Che-Ya CHOU, Wen-Chou WU, Yen-Ju LU, Chih-Ming HUNG, Wei-Hsiu HSU
  • Publication number: 20190035736
    Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.
    Type: Application
    Filed: February 23, 2018
    Publication date: January 31, 2019
    Inventors: Fu-Chiang KUO, Tao-Cheng Liu, Shih-Chi Kuo, Tsung-Hsien Lee
  • Patent number: 10186488
    Abstract: A manufacturing method of a semiconductor package includes the follow steps. Firstly, a carrier is provided. Then, a package substrate is formed. Then, a first electronic component is disposed above the second conductive layer of the package substrate. Then, a second package body encapsulating the first electronic component and the second conductive layer is formed. Then, the carrier is carried. Wherein in the step of forming the package substrate includes a step of forming a first conductive layer on the carrier, a step of forming a first pillar layer on the first conductive layer, a step of forming a first package body encapsulating the first conductive layer and the first pillar layer and a step of forming a second conductive layer on the first pillar layer.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: January 22, 2019
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng, Andrew C. Chang
  • Publication number: 20180366537
    Abstract: Methods of manufacturing trench capacitors include forming a trench opening in a substrate, depositing a first dielectric layer over a sidewall and a bottom surface of a first trench opening in a substrate, and depositing a first conductive layer over the first dielectric layer. The first dielectric layer and the first conductive layer are then planarized to expose a planarized top surface of the substrate and a planarized top surface of the first conductive layer in the first trench opening. An ILD layer is deposited over the planarized top surface of the substrate and over the planarized surface of the first conductive layer. A first electrical contact is formed through the ILD layer to provide an electrical connection to the first conductive layer within the first trench opening.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Inventors: Tao-Cheng LIU, Shih-Chi KUO, Tsai-Hao HUNG, Tsung-Hsien LEE
  • Publication number: 20180349539
    Abstract: A model including a first co-simulation component and a second co-simulation component is analyzed. During execution of the model, the first co-simulation component outputs data to the second co-simulation component via a connection. The connection is declared as a continuous-time rate connection for input of the data into the second co-simulation component. Based on analyzing the model, the connection is identified as a discrete-continuous sample time connection based on data being communicated from the first co-simulation component to the second co-simulation component via the connection at a discrete-time rate when the model is executed in a co-simulation manner.
    Type: Application
    Filed: June 2, 2017
    Publication date: December 6, 2018
    Inventors: Tao CHENG, Pieter J. MOSTERMAN, Haihua FENG, Fu ZHANG
  • Patent number: D865034
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: October 29, 2019
    Assignee: popln Inc.
    Inventor: Tao Cheng