Abstract: The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.

Abstract: Latch-up test device and method are provided, and the method includes following steps. A set operation is performed for setting a basic test value according to a test range and setting a trigger pulse and a predetermined error value by the basic test value. A test on a test chip in a wafer under test is performed by the trigger pulse, and whether the test chip is in a latch-up state is determined. Whether to update a test range and a latch-up threshold value and whether to return to the step of performing the set operation are determined according to a determination result, the latch-up threshold value and the basic test value. When the test chip is in the latch-up state and a difference between the latch-up threshold value and the basic test value is not greater than the predetermined error value, the test on the test chip is stopped.

Abstract: The present invention provides a resin composition comprising: 1 to 20 parts by weight of a reinforcing fiber; 0.2 to 5 parts by weight of an anti-settling agent; 20 to 40 parts by weight of an epoxy resin; 0.1 to 3 parts by weight of a curing agent; and 50 to 75 parts by weight of a high dielectric constant filler. The present invention further provides a dielectric layer produced from the resin composition and a capacitor comprising the dielectric layer. In the dielectric layer made from the resin composition provided by the present invention, the fibers can be evenly dispersed and can enhance the mechanical strength of the resin composition, and cooperate with the epoxy resin to bring excellent toughness. Therefore, the mechanical strength of the produced dielectric layer can be remarkably improved, and its fragility can be effectively overcome when the dielectric layer is used in the PCB double-side etching process.

Abstract: An electrostatic discharge protection device including a PNP transistor, a protection circuit and an adjustment circuit is provided. An emitter of the PNP transistor is electrically connected to a pad, and a collector of the PNP transistor is electrically connected to a ground. The protection circuit is electrically connected between a base of the PNP transistor and the ground, and provides a discharge path. When an electrostatic signal occurs on the pad, the electrostatic signal is conducted to the ground through the discharge path and the PNP transistor. The adjustment circuit is electrically connected between the emitter and the base of the PNP transistor. When a power voltage is supplied to the pad, the adjustment circuit provides a control voltage to the base of the PNP transistor according to the power voltage, so as to prevent the emitter and the base of the PNP transistor from being forward biased.

Abstract: A touch mouse including a pressure sensing region, a touch sensing region, and a control unit is disclosed. The pressure sensing region is disposed at a first side and a second side of the touch mouse, and the touch sensing region covers at least the pressure sensing region at the first side. The first side is opposite to the second side. When the user clicks the pressure sensing region, it generates a pressure sensing signal. When the user clicks the touch sensing region, it generates a touch sensing signal. When the pressure sensing signal and the touch sensing signal are generated, the control unit outputs a first clicking signal representing that the first side is clicked. When the pressure sensing signal is generated but the touch sensing signal is not, the control unit outputs a second clicking signal representing that the second side is clicked.

Abstract: A semiconductor device manufacturing method includes preparing a wafer having projections formed on a substrate. The projections project upward from a surface of the substrate and have a height measured from the surface of the substrate. The method further includes determining an interval distribution representing a distribution of intervals between neighboring projections and calculating an implantation angle based on the height and the interval distribution. The implantation angle is an angle between a normal direction of the substrate and an implantation direction. The method also includes implanting ions at the calculated implantation angle.

Abstract: The present invention provides a resin composition comprising: 1 to 20 parts by weight of a reinforcing fiber; 0.2 to 5 parts by weight of an anti-settling agent; 20 to 40 parts by weight of an epoxy resin; 0.1 to 3 parts by weight of a curing agent; and 50 to 75 parts by weight of a high dielectric constant filler. The present invention further provides a dielectric layer produced from the resin composition and a capacitor comprising the dielectric layer. In the dielectric layer made from the resin composition provided by the present invention, the fibers can be evenly dispersed and can enhance the mechanical strength of the resin composition, and cooperate with the epoxy resin to bring excellent toughness. Therefore, the mechanical strength of the produced dielectric layer can be remarkably improved, and its fragility can be effectively overcome when the dielectric layer is used in the PCB double-side etching process.

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.

Abstract: A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.

Abstract: Provided is a semiconductor device. Two stack layers are disposed on a substrate of a first conductivity type. Each of stack layers includes a dielectric layer and a conductive layer. The dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. First doped region of a second conductivity type has a first dopant and is disposed in the substrate between the stack layers. A pre-amorphization implantation (PAI) region is disposed in the first doped region. A second doped region of the second conductivity type has a second dopant and is disposed in the PAI region. The first conductivity type is different from the second conductivity type. A diffusion rate of the second dopant is faster than a diffusion rate of the first dopant, and a thermal activation of the second dopant is higher than that of the first dopant.

Abstract: A programming method of a memory array is provided and includes following steps, wherein the memory array includes a target memory cell and two periphery memory cells electrically connected to a first word line. After a first programming operation is performed on the target memory cell, the target memory cell and the two periphery memory cells are verified to obtain a first verification result. Whether to perform a second programming operation or a third programming operation on the target memory cell is determined according to the first verification result. The step of performing the second programming operation or the third programming operation on the target memory cell includes: turning off a first transistor and a second transistor; and increasing a level of a passing voltage for turning on a plurality of non-target memory cells and a level of a programming voltage transmitted by the first word line.

Abstract: A pre-processing method for video data playback and a playback interface apparatus are provided, wherein a video receiver module receives a video data with clips, the clips corresponding to numbers in first and second time-sequences, and wherein a display module creates a corresponding GUI component for each clip and arranges the GUI components in the playback interface. When two clips consecutive in the first time-sequence are not consecutive in the second, the display module places their corresponding GUI components separately or distinguishably. By discerning the several time-sequences of the video data, this invention ensures random access of data while being visually intuitive and uniform design-wise.

Abstract: An electrostatic discharge protection device that includes a plurality of voltage drop elements, an impedance element, a driving circuit, and a clamping circuit is provided. The voltage drop elements are electrically connected in series between a first line and a node, and the voltage drop elements are configured to define an activating voltage. If a signal from the first line is greater than the activating voltage, the voltage drop elements conduct the first line to the node in response to the signal from the first line. The impedance element is electrically connected between the node and a second line. The driving circuit amplifies a control signal from the node and accordingly generates a driving signal. The clamping circuit determines whether to generate a discharging path between the first line and the second line according to the driving signal.

Abstract: A semiconductor device manufacturing method includes preparing a wafer having projections formed on a substrate. The projections project upward from a surface of the substrate and have a height measured from the surface of the substrate. The method further includes determining an interval distribution representing a distribution of intervals between neighboring projections and calculating an implantation angle based on the height and the interval distribution. The implantation angle is an angle between a normal direction of the substrate and an implantation direction. The method also includes implanting ions at the calculated implantation angle.

Abstract: A computer-implemented method for detecting malicious use of digital certificates may include determining that a digital certificate is invalid. The method may further include locating, within the invalid digital certificate, at least one field that was previously identified as being useful in distinguishing malicious use of invalid certificates from benign use of invalid certificates. The method may also include determining, based on analysis of information from the field of the invalid digital certificate, that the invalid digital certificate is potentially being used to facilitate malicious communications. The method may additionally include performing a security action in response to determining that the invalid digital certificate is potentially being used to facilitate malicious communications. Various other methods, systems, and computer-readable media are disclosed.

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer.

Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a first package which includes at least a semiconductor die, a dielectric structure surrounding the semiconductor die, and a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die. The package structure also includes an interposer substrate over the first package and a plurality of conductive features in or over the interposer substrate. The package structure further includes a second package over the interposer substrate, and the first package electrically couples the second package through the conductive structures and the conductive features.

Abstract: A computer system and a method for adaptive thermal resistance-capacitance (RC) network analysis of a semiconductor device for use in a portable device are provided. The method includes the steps of: receiving a device input file and a plurality of specific effective heat transfer coefficients (HTCs) associated with the portable device; repeatedly performing a thermal analysis of the portable device based on the device input file and a current effective HTC to estimate a target die temperature of the semiconductor device; calculating a target effective HTC based on the device input file and the target die temperature; and updating the current effective HTC with the target effective HTC; and generating an output file recording the target die temperature of the semiconductor device.

Abstract: Provided is a semiconductor device. Two stack layers are disposed on a substrate of a first conductivity type. Each of stack layers includes a dielectric layer and a conductive layer. The dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. First doped region of a second conductivity type has a first dopant and is disposed in the substrate between the stack layers. A pre-amorphization implantation (PAI) region is disposed in the first doped region. A second doped region of the second conductivity type has a second dopant and is disposed in the PAI region. The first conductivity type is different from the second conductivity type. A diffusion rate of the second dopant is faster than a diffusion rate of the first dopant, and a thermal activation of the second dopant is higher than that of the first dopant.