Patents by Inventor Tatsuo Nishizawa

Tatsuo Nishizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055391
    Abstract: A method for manufacturing a semiconductor module can prevent performance and reliability degradation of a semiconductor module. The method for manufacturing a semiconductor module includes: arranging an insulating wiring board on a low die; arranging a sintering material at plural locations on the insulating wiring board and arranging a semiconductor chip on each of the plural sintering materials; arranging a structure above protruding portions of the sintering materials protruding from a periphery of each of the plural semiconductor chips; and sintering by pressurizing and heating the plural sintering materials by an upper die through the structure at the protruding portions and through the semiconductor chips at contacting portions in contact with lower surfaces of the semiconductor chips.
    Type: Application
    Filed: June 29, 2023
    Publication date: February 15, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuo NISHIZAWA
  • Publication number: 20240055422
    Abstract: A method for manufacturing a semiconductor module includes arranging an insulating wiring board on a lower die, arranging sintered materials at a plurality of points on the insulating wiring board, arranging each semiconductor chip on the sintered materials, arranging each buffer material individually on the semiconductor chips, arranging, above the lower die, an upper die including protrusions at points corresponding to arrangement positions of the semiconductor chips so that the protrusions correspond to the semiconductor chips, and sintering by pressurizing and heating the sintered materials by the protrusions through the buffer materials and the semiconductor chips.
    Type: Application
    Filed: June 29, 2023
    Publication date: February 15, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuo NISHIZAWA
  • Publication number: 20230307400
    Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a sintered metal such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 28, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi KATO, Yoshinari IKEDA, Tatsuo NISHIZAWA, Eiji MOCHIZUKI
  • Patent number: 11705419
    Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a metal sintered material such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: July 18, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yoshinari Ikeda, Tatsuo Nishizawa, Eiji Mochizuki
  • Patent number: 11545409
    Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: January 3, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yoshinari Ikeda, Tatsuo Nishizawa, Motohito Hori, Eiji Mochizuki
  • Patent number: 11171078
    Abstract: A semiconductor device includes an insulated circuit board having conductor layers arranged away from each other and bonding materials each provided on the conductor layers; a wiring board having an opposing surface facing the conductor layers and through holes each corresponding to a position of each bonding material; hollow members each having a cylindrical portion and a flanged portion at one end of the cylindrical portion and having a cavity in common with the cylindrical portion, ok cylindrical portions press-fitted into the through holes, and other ends of the cylindrical portions bonded to the conductor layers by the bonding materials; and external connection terminals each inserted into the cavity of each hollow member and bonded to the conductor layers. Each cylindrical portion is inserted into each through hole such that each flanged portion contacts with an upper surface opposed to the opposing surface of the wiring board.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: November 9, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichiro Hinata, Tatsuo Nishizawa
  • Patent number: 11133609
    Abstract: A semiconductor device includes: an insulation circuit substrate including a metal layer and an insulation substrate, the metal layer being formed on one surface of the insulation substrate, a connecting member having a cylindrical shape joined to the metal layer via a bonding material, a terminal pin inserted in the connecting member, and a reinforcement member having a cylindrical shape disposed on an outer periphery of the connecting member. The reinforcement member is made of a material having a hardness greater than that of the connecting member.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: September 28, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichiro Hinata, Tatsuo Nishizawa
  • Publication number: 20210242156
    Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a metal sintered material such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.
    Type: Application
    Filed: December 31, 2020
    Publication date: August 5, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi KATO, Yoshinari IKEDA, Tatsuo NISHIZAWA, Eiji MOCHIZUKI
  • Publication number: 20210242103
    Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.
    Type: Application
    Filed: January 5, 2021
    Publication date: August 5, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi KATO, Yoshinari IKEDA, Tatsuo NISHIZAWA, Motohito HORI, Eiji MOCHIZUKI
  • Patent number: 11037848
    Abstract: A semiconductor module includes block-shaped first and second lower base members provided by bonding of flat lower surfaces on an insulated circuit board and having bottomed first and second hole portions open in upper surfaces in upper portions of the first and second lower base members, tubular first and second upper slide support members inserted in the first and second hole portions in a state where at least a part of outside surfaces is in contact with inside walls of the first and second hole portions, first and second pins inserted in contact with the insides of the first and second upper slide support members, and a sealing resin sealing the first and second pins except for the upper portions of the first and second pins.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 15, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuhei Nishida, Tatsuo Nishizawa
  • Patent number: 10991650
    Abstract: A semiconductor device includes a conductive plate to which a semiconductor element is mounted on a front surface; a sealing resin internally encapsulating at least the front surface of the conductive plate and the semiconductor element; and an external connection terminal connected to the conductive plate and exposed outside the sealing resin. The external connection terminal has a buckling portion or an expanding and contracting portion. The external connection terminal may have a notch and the buckling portion is a part having the notch.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: April 27, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuo Nishizawa
  • Patent number: 10923414
    Abstract: A semiconductor device includes: an insulated circuit board including metal layers having recesses, and an insulating board having an upper surface on which the metal layers are arranged; external terminals having bottom ends with a width narrower than the width of openings of the recesses, these bottom ends being inserted into the recesses; a printed circuit board that directly supports the external terminals; and first bonding material that is arranged inside the recesses and respectively conductively connects the bottom ends of the external terminals to the metal layers.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: February 16, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hideyo Nakamura, Tatsuo Nishizawa
  • Publication number: 20210020554
    Abstract: A semiconductor device includes an insulated circuit board having conductor layers arranged away from each other and bonding materials each provided on the conductor layers; a wiring board having an opposing surface facing the conductor layers and through holes each corresponding to a position of each bonding material; hollow members each having a cylindrical portion and a flanged portion at one end of the cylindrical portion and having a cavity in common with the cylindrical portion, ok cylindrical portions press-fitted into the through holes, and other ends of the cylindrical portions bonded to the conductor layers by the bonding materials; and external connection terminals each inserted into the cavity of each hollow member and bonded to the conductor layers. Each cylindrical portion is inserted into each through hole such that each flanged portion contacts with an upper surface opposed to the opposing surface of the wiring board.
    Type: Application
    Filed: February 26, 2020
    Publication date: January 21, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichiro HINATA, Tatsuo NISHIZAWA
  • Patent number: 10636316
    Abstract: An education support system provides information that helps educators and students to achieve effective and efficient learning. The system includes a plurality of terminal devices and a server. The terminal devices include a terminal display unit, voice output unit, reproduction log data memory unit, and transmission unit. The server includes a digital content memory unit that stores digital content received from the terminal devices, a receiver unit that receives the reproduction log data transmitted from the respective terminal devices, a data conversion unit, a server display unit; and a display control unit that arranges strings of phrases in the reproduction log data in a vertical direction, displays times spent on reproduction of the strings of the phrases to be displayed with the lateral length of the squares on a right side of the respective strings, and displays number of times of reproduction by phrase on the same screen.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: April 28, 2020
    Assignee: SHINANO KENSHI KABUSHIKI KAISHA
    Inventors: Tatsuo Nishizawa, Yusuke Tashiro
  • Publication number: 20200091634
    Abstract: A semiconductor device includes: an insulation circuit substrate including a metal layer and an insulation substrate, the metal layer being formed on one surface of the insulation substrate, a connecting member having a cylindrical shape joined to the metal layer via a bonding material, a terminal pin inserted in the connecting member, and a reinforcement member having a cylindrical shape disposed on an outer periphery of the connecting member. The reinforcement member is made of a material having a hardness greater than that of the connecting member.
    Type: Application
    Filed: July 26, 2019
    Publication date: March 19, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichiro HINATA, Tatsuo NISHIZAWA
  • Patent number: 10446460
    Abstract: The semiconductor device includes a first insulating circuit substrate; a semiconductor chip including a plurality of control electrodes, disposed on the first insulating circuit substrate; a second insulating circuit substrate including a plurality of first through-holes in which conductive members are arranged on inner walls and/or an outer periphery of ends of the first through-holes, the second insulating circuit substrate being disposed above the semiconductor chips; and first pins inserted into the first through-holes and having at one end a columnar part connected to the control electrodes of the semiconductor chips, and having at another end a head part that is wider than an inner diameter of the first through-holes.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: October 15, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiromichi Gohara, Kohei Yamauchi, Shinji Tada, Tatsuo Nishizawa, Yoshitaka Nishimura
  • Publication number: 20190287887
    Abstract: A semiconductor device includes: an insulated circuit board including metal layers having recesses, and an insulating board having an upper surface on which the metal layers are arranged; external terminals having bottom ends with a width narrower than the width of openings of the recesses, these bottom ends being inserted into the recesses; a printed circuit board that directly supports the external terminals; and first bonding material that is arranged inside the recesses and respectively conductively connects the bottom ends of the external terminals to the metal layers.
    Type: Application
    Filed: February 6, 2019
    Publication date: September 19, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Hideyo NAKAMURA, Tatsuo NISHIZAWA
  • Publication number: 20190273041
    Abstract: A semiconductor device includes a conductive plate to which a semiconductor element is mounted on a front surface; a sealing resin internally encapsulating at least the front surface of the conductive plate and the semiconductor element; and an external connection terminal connected to the conductive plate and exposed outside the sealing resin. The external connection terminal has a buckling portion or an expanding and contracting portion. The external connection terminal may have a notch and the buckling portion is a part having the notch.
    Type: Application
    Filed: January 30, 2019
    Publication date: September 5, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuo NISHIZAWA
  • Publication number: 20190189529
    Abstract: A semiconductor module includes block-shaped first and second lower base members provided by bonding of flat lower surfaces on an insulated circuit board and having bottomed first and second hole portions open in upper surfaces in upper portions of the first and second lower base members, tubular first and second upper slide support members inserted in the first and second hole portions in a state where at least a part of outside surfaces is in contact with inside walls of the first and second hole portions, first and second pins inserted in contact with the insides of the first and second upper slide support members, and a sealing resin sealing the first and second pins except for the upper portions of the first and second pins.
    Type: Application
    Filed: November 28, 2018
    Publication date: June 20, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yuhei NISHIDA, Tatsuo NISHIZAWA
  • Patent number: 10297165
    Abstract: To provide an education support system that allows educators to conduct adequate assessments considering handicaps or characteristics of individual students and to offer effective and efficient learning.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: May 21, 2019
    Assignee: SHINANO KENSHI KABUSHIKI KAISHA
    Inventors: Tatsuo Nishizawa, Yusuke Tashiro