Patents by Inventor Tatsuo Shimizu

Tatsuo Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11563090
    Abstract: According to an embodiment of the invention, a semiconductor device includes a base body that includes silicon carbide, a first semiconductor member that includes silicon carbide and is of a first conductivity type, and a second semiconductor member that includes silicon carbide and is of a second conductivity type. A first direction from the base body toward the first semiconductor member is along a [0001] direction of the base body. The second semiconductor member includes a first region, a second region, and a third region. The first semiconductor member includes a fourth region. A second direction from the first region toward the second region is along a [1-100] direction of the base body. The fourth region is between the first region and the second region in the second direction. A third direction from the fourth region toward the third region is along a [11-20] direction of the base body.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: January 24, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Johji Nishio, Tatsuo Shimizu
  • Publication number: 20220416030
    Abstract: This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z1/2 in a portion is not more than 1×1011 cm?3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×1018 cm?3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×1018 cm?3.
    Type: Application
    Filed: September 2, 2022
    Publication date: December 29, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Johji NISHIO, Chiharu OTA, Toshihide ITO
  • Patent number: 11532721
    Abstract: According to an embodiment, provided is a semiconductor device including: a first electrode; a second electrode; and a silicon carbide layer disposed between the first electrode and the second electrode, the silicon carbide layer including: a first silicon carbide region of an n-type; and a second silicon carbide region disposed between the first silicon carbide region and the first electrode, the second silicon carbide being in contact with the first electrode, and the second silicon carbide containing one oxygen atom bonding with four silicon atoms.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: December 20, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Shimizu
  • Publication number: 20220393008
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a first conductive member, a semiconductor member, and a first insulating member. The third electrode includes a third electrode end portion and a third electrode other end portion. The third electrode end portion is between the first electrode and the third electrode other end portion. The first conductive member includes a first conductive member end portion and a first conductive member other end portion. The first conductive member end portion is between the first electrode and the first conductive member other end portion. The semiconductor member includes first to third semiconductor regions. The first semiconductor region includes first and second partial regions. The first insulating member includes silicon and oxygen. The first insulating member includes a first element including at least one selected from the group consisting of nitrogen, aluminum, hafnium and zirconium at the third position.
    Type: Application
    Filed: January 27, 2022
    Publication date: December 8, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke KOBAYASHI, Tatsuo SHIMIZU, Tomoaki INOKUCHI, Hiro GANGI, Hiroki NEMOTO
  • Patent number: 11515468
    Abstract: Provided is a piezoelectric ceramics having a gradual change in piezoelectric constant depending on an ambient temperature. Specifically, provided is a single-piece piezoelectric ceramics including as a main component a perovskite-type metal oxide represented by a compositional formula of ABO3, wherein an A site element in the compositional formula contains Ba and M1, the M1 being formed of at least one kind selected from the group consisting of Ca and Bi, wherein a B site element in the compositional formula contains T1 and M2, the M2 being formed of at least one kind selected from the group consisting of Zr, Sn, and Hf, wherein concentrations of the M1 and the M2 change in at least one direction of the piezoelectric ceramics, and wherein increase and decrease directions of concentration changes of the M1 and the M2 are directions opposite to each other.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: November 29, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Makoto Kubota, Yasushi Shimizu, Takanori Matsuda, Tatsuo Furuta, Kaoru Miura, Miki Ueda, Kanako Oshima
  • Publication number: 20220363057
    Abstract: The diaphragm includes a first layer containing silicon as a constituent element, a third layer disposed between the first layer and the piezoelectric actuator and containing zirconium as a constituent element, and a second layer disposed between the first layer and the third layer and containing at least one selected from the group consisting of a metal other than iron, silicon, and zirconium, a metalloid, and a semiconductor, as a constituent element, in the second layer and the third layer, a position with a highest concentration of impurities other than the constituent elements of the second layer and the third layer is in the second layer, a position with a highest concentration of zirconium is in the third layer, and a position with a highest concentration of silicon is in the first layer.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 17, 2022
    Inventors: Harunobu KOIKE, Tatsuo SAWASAKI, Masao NAKAYAMA, Toshihiro SHIMIZU, Chihiro NISHI
  • Patent number: 11502173
    Abstract: A semiconductor device according to embodiments includes a gate electrode; a gate insulating layer; and a silicon carbide layer having a first plane and a second plane facing the first plane, the silicon carbide layer including a first silicon carbide region of p-type and a second silicon carbide region positioned between the first silicon carbide region and the gate insulating layer, and the second silicon carbide region including at least one oxygen atom bonded to four silicon atoms.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: November 15, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Shimizu
  • Publication number: 20220324231
    Abstract: A substrate having a recessed portion, a diaphragm, and a piezoelectric actuator are provided, the diaphragm includes a first layer containing silicon as a constituent element, and a third layer disposed between the first layer and the piezoelectric actuator and containing zirconium as a constituent element, and a laminated side surface of the first layer and the third layer is covered with a moisture-resistant protective film containing at least one selected from the group made of oxide, nitride, metal, and diamond-like carbon.
    Type: Application
    Filed: March 28, 2022
    Publication date: October 13, 2022
    Inventors: Harunobu KOIKE, Tatsuo SAWASAKI, Masao NAKAYAMA, Toshihiro SHIMIZU
  • Patent number: 11469301
    Abstract: This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z1/2 in a portion is not more than 1×1011 cm?3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×1018 cm?3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×1018 cm?3.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: October 11, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
  • Publication number: 20220314621
    Abstract: A substrate, a diaphragm, and a piezoelectric actuator are laminated in this order in a first direction, the diaphragm includes a first layer containing silicon as a constituent element, a second layer disposed between the first layer and the piezoelectric actuator, and containing any one or both of at least one metal element selected from the group made of chromium, titanium, aluminum, tantalum, hafnium, and iridium, and silicon nitride, as a constituent element, and a third layer disposed between the second layer and the piezoelectric actuator and containing zirconium as a constituent element, and a fourth layer containing any one or both of at least one metal element selected from the group made of chromium, titanium, aluminum, tantalum, hafnium, and iridium, and silicon nitride, as a constituent element is provided on the third layer on a piezoelectric actuator side.
    Type: Application
    Filed: March 28, 2022
    Publication date: October 6, 2022
    Inventors: Harunobu KOIKE, Masao NAKAYAMA, Toshihiro SHIMIZU, Yasushi YAMAZAKI, Osamu TONOMURA, Tatsuo SAWASAKI, Chihiro NISHI
  • Publication number: 20220310791
    Abstract: A semiconductor device of embodiments includes: a silicon carbide layer having a first face and a second face and including a first trench, a second trench having a distance of 100 nm or less from the first trench, a first silicon carbide region of n-type, a second silicon carbide region of p-type between the first trench and the second trench, a third silicon carbide region of n-type between the second silicon carbide region and the first face, a fourth silicon carbide region between the first trench and the second silicon carbide region and containing oxygen, and a fifth silicon carbide region between the second trench and the second silicon carbide region and containing oxygen; a first gate electrode in the first trench; a second gate electrode in the second trench; a first gate insulating layer; a second gate insulating layer; a first electrode; and a second electrode.
    Type: Application
    Filed: September 8, 2021
    Publication date: September 29, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo SHIMIZU
  • Publication number: 20220302261
    Abstract: A semiconductor device of embodiments includes: a silicon carbide layer having a first face having an off-angle of 0° or more and 8° or less with respect to a {0001}face and a second face opposite to the first face, having a 4H-SiC crystal structure, and including a first silicon carbide region of p-type, a second silicon carbide region of n-type between the first silicon carbide region and the first face, and a third silicon carbide region between the first silicon carbide region and the first face and containing oxygen, the second silicon carbide region disposed between the third silicon carbide region and the first face; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration of 1×1021 cm?3 or more.
    Type: Application
    Filed: September 7, 2021
    Publication date: September 22, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo SHIMIZU
  • Publication number: 20220302250
    Abstract: A semiconductor device of embodiments includes: a silicon carbide layer having a first face and a second face opposite to the first face, and including a p-type silicon carbide region in contact with the first face, a percentage of a first silicon atom among a plurality of silicon atoms present in a first layer as an uppermost layer being equal to or more than 90% and a site position of the first silicon atom being different from a site position of a silicon atom in a third layer from the first face and the same as a site position of a silicon atom in a fifth layer from the first face; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer including nitrogen.
    Type: Application
    Filed: September 7, 2021
    Publication date: September 22, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo SHIMIZU
  • Patent number: 11450745
    Abstract: A semiconductor device according to embodiments includes a p-type SiC region, a gate insulating film disposed on the p-type SiC region, and a gate electrode disposed on the gate insulating film and including a p-type impurity and 3C—SiC.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: September 20, 2022
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Johji Nishio, Takashi Shinohe
  • Patent number: 11450746
    Abstract: A semiconductor device of an embodiment includes a first electrode; a second electrode; and a silicon carbide layer disposed between the first electrode and the second electrode, and includes a first silicon carbide region of n-type; and a second silicon carbide region disposed between the first silicon carbide region and the first electrode, in contact with the first electrode, containing an at least one element selected from the group consisting of sulfur (S), selenium (Se), tellurium (Te), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), and tungsten (W), and containing at least one first atom of the at least one element, the first atom being bonded to four silicon atoms.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: September 20, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Shimizu
  • Patent number: 11424327
    Abstract: A semiconductor device of an embodiment includes an electrode; and a silicon carbide layer in contact with the electrode and including: a first silicon carbide region of n-type; and a second silicon carbide region disposed between the first silicon carbide region and the electrode, in contact with the electrode, and containing at least one oxygen atom bonded to four carbon atoms.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: August 23, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Shimizu
  • Patent number: 11424326
    Abstract: According to one embodiment, a semiconductor device includes a silicon carbide member, first, second, and third electrodes, and a first insulating member. The silicon carbide member includes first, second, and third silicon carbide regions. The first silicon carbide region includes first, second, third, and fourth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the third partial region and the first electrode. The second silicon carbide region includes first and second semiconductor regions. The third silicon carbide region includes third and fourth semiconductor regions. The first insulating member includes first, second, and third insulating regions. The second electrode is electrically connected to the first silicon carbide region. The third and fourth partial regions are between the second and first electrodes. The third electrode is electrically connected to the second silicon carbide region.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: August 23, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukio Nakabayashi, Tatsuo Shimizu, Toshihide Ito, Chiharu Ota, Johji Nishio
  • Publication number: 20220262916
    Abstract: A semiconductor device of an embodiment includes: a silicon carbide layer including a first silicon carbide region of n-type containing one metal element selected from a group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr) and a second silicon carbide region of p-type containing the metal element; and a metal layer electrically connected to the first silicon carbide region and the second silicon carbide region. Among the metal elements contained in the first silicon carbide region, a proportion of the metal element positioned at a carbon site is higher than a proportion of the metal element positioned at an interstitial position. Among the metal elements contained in the second silicon carbide region, a proportion of the metal element positioned at an interstitial position is higher than a proportion of the metal element positioned at a carbon site.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 18, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo SHIMIZU
  • Patent number: 11362174
    Abstract: A method of manufacturing semiconductor device of an embodiment includes performing a first ion implantation implanting at least one element selected from a group consisting of beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), zinc (Zn), cadmium (Cd), silicon (Si), germanium (Ge), and tin (Sn) into a nitride semiconductor layer; performing a second ion implantation implanting nitrogen (N) into the nitride semiconductor layer; performing a third ion implantation implanting hydrogen (H) into the nitride semiconductor layer; forming a covering layer on a surface of the nitride semiconductor layer after the first ion implantation, the second ion implantation, and the third ion implantation; performing a first heat treatment after forming the covering layer; removing the covering layer after the first heat treatment; and performing a second heat treatment after removing the covering layer.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: June 14, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Shimizu
  • Patent number: 11355612
    Abstract: A semiconductor device of an embodiment includes: a silicon carbide layer including a first silicon carbide region of n-type containing one metal element selected from a group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr) and a second silicon carbide region of p-type containing the metal element; and a metal layer electrically connected to the first silicon carbide region and the second silicon carbide region. Among the metal elements contained in the first silicon carbide region, a proportion of the metal element positioned at a carbon site is higher than a proportion of the metal element positioned at an interstitial position. Among the metal elements contained in the second silicon carbide region, a proportion of the metal element positioned at an interstitial position is higher than a proportion of the metal element positioned at a carbon site.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: June 7, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Shimizu