Patents by Inventor Tatsuo Shimizu
Tatsuo Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230299152Abstract: Provided is a method for manufacturing a semiconductor device, the method including: performing first ion implantation ion-implanting a p-type impurity into a silicon carbide layer; performing second ion implantation ion-implanting carbon (C) into the silicon carbide layer; performing a first heat treatment activating the p-type impurity; performing a first oxidation treatment oxidizing the silicon carbide layer; performing an etching treatment etching the silicon carbide layer in an atmosphere containing hydrogen gas; forming a first metal film containing at least one metal element selected from the group consisting of nickel, palladium, platinum, and chromium; performing a second heat treatment causing the silicon carbide layer to react with the first metal film to form a metal silicide layer containing the at least one metal element; and forming a second metal film having a chemical composition different from a chemical composition of the first metal film.Type: ApplicationFiled: August 29, 2022Publication date: September 21, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tatsuo SHIMIZU
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Patent number: 11764269Abstract: This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z1/2 in a portion is not more than 1×1011 cm?3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×1018 cm?3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×1018 cm?3.Type: GrantFiled: September 2, 2022Date of Patent: September 19, 2023Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
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Patent number: 11764270Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. Nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3, and a carbon concentration at the position is equal to or less than 1×1018 cm?3.Type: GrantFiled: August 13, 2020Date of Patent: September 19, 2023Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
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Patent number: 11764059Abstract: According to one embodiment, a method for manufacturing a substrate is disclosed. The method can include preparing a structure body. The structure body includes a first semiconductor member and a second semiconductor member. The first semiconductor member includes silicon carbide including a first element. The second semiconductor member includes silicon carbide including a second element. The first element includes at least one selected from a first group consisting of N, P, and As. The second element includes at least one selected from a second group consisting of B, Al, and Ga. The method can include forming a hole that extends through the second semiconductor member and reaches the first semiconductor member. In addition, the method can include forming a third semiconductor member in the hole. The third semiconductor member includes silicon carbide including a third element. The third element includes at least one selected from the first group.Type: GrantFiled: September 8, 2020Date of Patent: September 19, 2023Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Johji Nishio, Tatsuo Shimizu
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Publication number: 20230253487Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, a first insulating member, and a nitride member. The third electrode includes a first electrode portion. A position of the first electrode portion is between a position of the first electrode and a position of the second electrode. The first semiconductor region includes first to fifth partial regions. A position of the fourth partial region is between positions of the first and third partial regions. A position of the fifth partial region is between positions of the third and second partial regions. The second semiconductor region includes first and second semiconductor portions. The first electrode portion is located between the first and second semiconductor portions. The first insulating member includes first to third insulating regions. The nitride member includes first to third nitride regions.Type: ApplicationFiled: August 5, 2022Publication date: August 10, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi ONO, Yosuke KAJIWARA, Daimotsu KATO, Masahiko KURAGUCHI, Tatsuo SHIMIZU
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Publication number: 20230207321Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1 × 1021 cm-3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1 × 1018 cm-3 and a carbon concentration at the first position is equal to or less than 1 × 1018 cm-3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1 × 1018 cm-3.Type: ApplicationFiled: February 21, 2023Publication date: June 29, 2023Applicant: Kabushiki Kaisha ToshibaInventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Johji NISHIO, Chiharu OTA, Toshihide ITO
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Publication number: 20230197790Abstract: A method for manufacturing a semiconductor device of an embodiment includes performing first ion implantation of implanting aluminum (Al) into a silicon carbide layer in a first projected range and a first dose amount, performing second ion implantation of implanting carbon (C) into the silicon carbide layer in a second projected range and a second dose amount which is a dose amount equal to or more than 10 times the first dose amount, performing a first heat treatment of 1600° C. or more, performing an oxidation treatment of oxidizing the silicon carbide layer, performing an etching process of etching the silicon carbide layer in an atmosphere containing a hydrogen gas, forming a silicon oxide film on the silicon carbide layer, and forming a gate electrode on the silicon oxide film.Type: ApplicationFiled: August 30, 2022Publication date: June 22, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Toshihide ITO, Chiharu OTA, Johji NISHIO
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Patent number: 11677009Abstract: A semiconductor device of an embodiment includes: a silicon carbide layer including a first silicon carbide region of n-type containing one metal element selected from a group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr) and a second silicon carbide region of p-type containing the metal element; and a metal layer electrically connected to the first silicon carbide region and the second silicon carbide region. Among the metal elements contained in the first silicon carbide region, a proportion of the metal element positioned at a carbon site is higher than a proportion of the metal element positioned at an interstitial position. Among the metal elements contained in the second silicon carbide region, a proportion of the metal element positioned at an interstitial position is higher than a proportion of the metal element positioned at a carbon site.Type: GrantFiled: May 2, 2022Date of Patent: June 13, 2023Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Tatsuo Shimizu
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Publication number: 20230154988Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a metal layer; and a conductive layer positioned between the silicon carbide layer and the metal layer, the conductive layer containing a silicide of one metal element (M) selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), and the conductive layer having a carbon concentration of 1×1017 cm?3 or less.Type: ApplicationFiled: January 20, 2023Publication date: May 18, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tatsuo SHIMIZU
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Publication number: 20230107057Abstract: According to one embodiment, a wafer includes a base body including a first surface, and a crystal layer provided on the first surface. The crystal layer includes first stacking faults and one or second stacking faults. One of the first stacking faults includes a first long side, a first short side, and a first hypotenuse. A position of the first long side in a first direction from the base body to the crystal layer is between the base body in the first direction and a first corner portion in the first direction. One of the one or the plurality of second stacking faults includes a second long side, a second short side, and a second hypotenuse. A position of a second corner portion in the first direction is between the base body in the first direction and the second long side in the first direction.Type: ApplicationFiled: July 13, 2022Publication date: April 6, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Johji NISHIO, Chiharu OTA, Tatsuo SHIMIZU, Ryosuke IIJIMA
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Patent number: 11621167Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3 and a carbon concentration at the first position is equal to or less than 1×1018 cm?3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm?3.Type: GrantFiled: January 5, 2022Date of Patent: April 4, 2023Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
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Publication number: 20230082881Abstract: A semiconductor device of embodiments includes: a silicon carbide layer having a first face having an off angle equal to or more than 0° and equal to or less than 8° with respect to a {0001} face and a second face facing the first face and having a 4H-SiC crystal structure; a gate electrode extending in a first direction parallel to the first face; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1 × 1021 cm-3. Assuming that a first reference length in the first direction is 0.5 µm, a surface roughness of a surface of the silicon carbide layer in a range of the first reference length is equal to or less than 1 nm.Type: ApplicationFiled: March 2, 2022Publication date: March 16, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tatsuo SHIMIZU
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Publication number: 20230084127Abstract: A semiconductor device manufacturing method of embodiments includes: forming a silicon oxide film on a surface of a silicon carbide layer; performing a first heat treatment in an atmosphere containing nitrogen gas at a temperature equal to or more than 1200° C. and equal to or less than 1600° C.; and performing a second heat treatment in an atmosphere containing nitrogen oxide gas at a temperature equal to or more than 750° C. and equal to or less than 1050° C.Type: ApplicationFiled: March 7, 2022Publication date: March 16, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Toshihide ITO, Chiharu OTA, Shigeto FUKATSU, Johji NISHIO, Ryosuke IIJIMA
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Publication number: 20230085364Abstract: A semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type including a first portion and a second portion, a second semiconductor layer of a second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, a gate electrode located between the second semiconductor region and the fourth semiconductor region and between the third semiconductor region and the fourth semiconductor region in a second direction, a first insulating region, a third electrode, and a second insulating region.Type: ApplicationFiled: February 18, 2022Publication date: March 16, 2023Applicant: Kabushiki Kaisha ToshibaInventors: Hiroki NEMOTO, Yusuke KOBAYASHI, Tomoaki INOKUCHI, Hiro GANGI, Tatsuo SHIMIZU
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Publication number: 20230081981Abstract: A semiconductor device manufacturing method of embodiments includes: performing first ion implantation implanting an element of either carbon (C) or oxygen (O) into a nitride semiconductor layer; performing second ion implantation implanting hydrogen (H) into the nitride semiconductor layer; forming a coating layer on a surface of the nitride semiconductor layer; performing a first heat treatment; removing the coating layer; and performing a second heat treatment.Type: ApplicationFiled: March 2, 2022Publication date: March 16, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tatsuo SHIMIZU
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Publication number: 20230078447Abstract: A semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a fourth semiconductor region of a second conductivity type, a third electrode connected to the second electrode and the fourth semiconductor region, a first insulating region, a gate electrode, and a second insulating region.Type: ApplicationFiled: February 18, 2022Publication date: March 16, 2023Applicant: Kabushiki Kaisha ToshibaInventors: Hiroki NEMOTO, Yusuke KOBAYASHI, Tomoaki INOKUCHI, Hiro GANGI, Tatsuo SHIMIZU
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Publication number: 20230079954Abstract: According to an embodiment, provided is a semiconductor device including: a first electrode; a second electrode; and a silicon carbide layer disposed between the first electrode and the second electrode, the silicon carbide layer including: a first silicon carbide region of an n-type; and a second silicon carbide region disposed between the first silicon carbide region and the first electrode, the second silicon carbide being in contact with the first electrode, and the second silicon carbide containing one oxygen atom bonding with four silicon atoms.Type: ApplicationFiled: November 16, 2022Publication date: March 16, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tatsuo SHIMIZU
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Publication number: 20230061811Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, first and second insulating members, a compound member, and a nitride member. The third electrode is between the first and second electrodes. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first to fifth partial regions. The second semiconductor region includes first and second semiconductor portions. The first insulating member includes first and second insulating portions. The first semiconductor portion is between the fourth partial region and the first insulating portion. The second semiconductor portion is between the fifth partial region and the second insulating portion. The compound member includes first to third compound portions. The nitride member includes first to third nitride portions. The second insulating member includes first and second insulating regions.Type: ApplicationFiled: March 1, 2022Publication date: March 2, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daimotsu KATO, Hiroshi ONO, Yosuke KAJIWARA, Aya SHINDOME, Akira MUKAI, Po-Chin HUANG, Masahiko KURAGUCHI, Tatsuo SHIMIZU
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Publication number: 20230068711Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, a first conductive member, first and second insulating members, and a first nitride member. A position of the third electrode in a first direction from the first to second electrodes is between positions of the first and second electrodes in the first direction. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first to fifth partial regions. The second semiconductor region includes first and second semiconductor portions. The second semiconductor portion includes first and second portions, and a third portion between the first and second portions. The first conductive member includes first and second conductive regions. The first insulating member includes a first insulating region. The second insulating member includes first and second insulating portions. The first nitride member includes a first nitride region.Type: ApplicationFiled: March 1, 2022Publication date: March 2, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daimotsu KATO, Yosuke KAJIWARA, Hiroshi ONO, Aya SHINDOME, Akira MUKAI, Po-Chin HUANG, Masahiko KURAGUCHI, Tatsuo SHIMIZU
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Publication number: 20230064469Abstract: According to one embodiment, a wafer includes a substrate and a crystal layer. The substrate includes a plurality of SiC regions including SiC and an inter-SiC region including Si provided between the SiC regions. The crystal layer includes a first layer, and a first intermediate layer provided between the substrate and the first layer in a first direction. The first layer includes SiC and nitrogen. The first intermediate layer includes SiC and nitrogen. A second concentration of nitrogen in the first intermediate layer is higher than a first concentration of nitrogen in the first layer.Type: ApplicationFiled: February 2, 2022Publication date: March 2, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuhiro KUSHIBE, Johji NISHIO, Ryosuke IIJIMA, Tatsuo SHIMIZU, Chiharu OTA, Shoko SUYAMA