Patents by Inventor Tatsuya Nishiwaki

Tatsuya Nishiwaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190259871
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having first and second surfaces and an impurity concentration distribution in a first direction from the second surface to the first surface, a first semiconductor region of a second conductivity between the semiconductor layer and the first surface, a second semiconductor region of a first conductivity type between the first semiconductor region and the first surface side, a first trench extending from the first surface into the semiconductor layer, a first electrode located in the first trench over a first insulating film and spaced from the first semiconductor region by a first insulating film, a second electrode located in the first trench over a second insulating film, a second trench extending from the first surface into the semiconductor layer and surrounding the first trench, and a third electrode located in the second trench over a third insulating film.
    Type: Application
    Filed: August 31, 2018
    Publication date: August 22, 2019
    Inventors: Hiroshi MATSUBA, Hung HUNG, Tatsuya NISHIWAKI, Kohei OASA, Kikuo AIDA
  • Publication number: 20190081173
    Abstract: A semiconductor device which includes a semiconductor layer, a first electrode, a second electrode, first trenches, a second trench surrounding the first trenches, a gate electrode and a first field plate electrode in the first trenches, a first insulating layer including a first portion p having a first film thickness, a second portion having a second film thickness thicker than the first film thickness, and a third portion having a third film thickness thicker than the second film thickness, a second field plate electrode in the second trench, a second insulating layer in the second trench. The semiconductor layer includes a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type, and a third semiconductor region having the second conductivity type.
    Type: Application
    Filed: February 23, 2018
    Publication date: March 14, 2019
    Inventors: Tatsuya NISHIWAKI, Kentaro ICHINOSEKI, Kikuo AIDA, Kohei OASA, Hung HUNG, Hiroshi MATSUBA
  • Publication number: 20190051760
    Abstract: A semiconductor device includes an anode electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a conductive portion and a cathode electrode. The first semiconductor region is electrically connected to the anode electrode. The second semiconductor region is provided on the first semiconductor region. The conductive portion is provided in the first semiconductor region and the second semiconductor region with an insulating layer interposed between the conductive portion and the first and second semiconductor regions. The cathode electrode is electrically connected to the conductive portions and is electrically isolated from the second semiconductor region.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 14, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuya Nishiwaki
  • Patent number: 10134921
    Abstract: A semiconductor device includes an anode electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a conductive portion and a cathode electrode. The first semiconductor region is electrically connected to the anode electrode. The second semiconductor region is provided on the first semiconductor region. The conductive portion is provided in the first semiconductor region and the second semiconductor region with an insulating layer interposed between the conductive portion and the first and second semiconductor regions. The cathode electrode is electrically connected to the conductive portions and is electrically isolated from the second semiconductor region.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: November 20, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuya Nishiwaki
  • Patent number: 10121892
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type on the first semiconductor region, a third semiconductor region of the first conductivity type on the second semiconductor region, a first electrode surrounded by the first semiconductor region, a first insulating portion between a first part of the first electrode and the first semiconductor region, a second insulating portion having a higher dielectric constant than the first insulating portion, between a second part of the first electrode and the first semiconductor region, a gate electrode above the first electrode, and a gate insulating portion between the second semiconductor region and the gate electrode.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: November 6, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuya Nishiwaki
  • Publication number: 20180240916
    Abstract: A semiconductor device includes an anode electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a conductive portion and a cathode electrode. The first semiconductor region is electrically connected to the anode electrode. The second semiconductor region is provided on the first semiconductor region. The conductive portion is provided in the first semiconductor region and the second semiconductor region with an insulating layer interposed between the conductive portion and the first and second semiconductor regions. The cathode electrode is electrically connected to the conductive portions and is electrically isolated from the second semiconductor region.
    Type: Application
    Filed: April 25, 2018
    Publication date: August 23, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuya NISHIWAKI
  • Patent number: 9978884
    Abstract: A semiconductor device includes an anode electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a conductive portion and a cathode electrode. The first semiconductor region is electrically connected to the anode electrode. The second semiconductor region is provided on the first semiconductor region. The conductive portion is provided in the first semiconductor region and the second semiconductor region with an insulating layer interposed between the conductive portion and the first and second semiconductor regions. The cathode electrode is electrically connected to the conductive portions and is electrically isolated from the second semiconductor region.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: May 22, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuya Nishiwaki
  • Publication number: 20180102308
    Abstract: In some embodiments, a semiconductor device includes a semiconductor chip including a first terminal, a second terminal and a third terminal, a frame electrically coupled to the second terminal, the frame mounting the semiconductor chip, a first conductor including a chip connection electrically coupled to the first terminal, a first connection connecting to the chip connection and protruding from the chip connection, and a second connection connecting to the chip connection, protruding from the chip connection, and being provided physically spaced from the first connection. The semiconductor device further includes a second conductor electrically coupled to the third terminal.
    Type: Application
    Filed: March 1, 2017
    Publication date: April 12, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuya NISHIWAKI, Shunsuke KATOH, Masatoshi ARAI, Chikako YOSHIOKA, Bungo TANAKA, Shinya OZAWA, Takahiro KAWANO
  • Publication number: 20180076338
    Abstract: A semiconductor device includes an anode electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a conductive portion and a cathode electrode. The first semiconductor region is electrically connected to the anode electrode. The second semiconductor region is provided on the first semiconductor region. The conductive portion is provided in the first semiconductor region and the second semiconductor region with an insulating layer interposed between the conductive portion and the first and second semiconductor regions. The cathode electrode is electrically connected to the conductive portions and is electrically isolated from the second semiconductor region.
    Type: Application
    Filed: March 2, 2017
    Publication date: March 15, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuya NISHIWAKI
  • Patent number: 9917183
    Abstract: A semiconductor device is provided including a first electrode and a first semiconductor layer of a first conductivity type connected to the first electrode. The semiconductor device further includes a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, and a second electrode provided on the third semiconductor layer. The semiconductor device further includes a third electrode disposed between the first electrode and the second electrode. The semiconductor device further includes a fourth electrode having an upper end connected to the second electrode, where the fourth electrode has a higher resistivity than the second electrode.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: March 13, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masatoshi Arai, Yoshitaka Hokomoto, Tatsuya Nishiwaki
  • Patent number: 9869014
    Abstract: A method for forming an alignment film for a liquid crystal on a substrate and an associated at least one structure. The substrate is moved in a first direction. A target is disposed on the first surface side of the substrate. The ion beam is propagated from an ion source toward the substrate and impinges on a sputtering surface of the target, which sputters a material of the target and results in sputtered particles of the material being emitted from the sputtering surface of the target and deposited on the first surface side of the substrate to form (i) a sputtering film on the first surface side of the substrate and (ii) an alignment film having an orientation and being disposed on the sputtering film and on the entire surface of the substrate. The alignment film aligns molecules of the liquid crystal in a predetermined direction.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Shoichi Doi, Tatsuya Nishiwaki
  • Publication number: 20170263767
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type on the first semiconductor region, a third semiconductor region of the first conductivity type on the second semiconductor region, a first electrode surrounded by the first semiconductor region, a first insulating portion between a first part of the first electrode and the first semiconductor region, a second insulating portion having a higher dielectric constant than the first insulating portion, between a second part of the first electrode and the first semiconductor region, a gate electrode above the first electrode, and a gate insulating portion between the second semiconductor region and the gate electrode.
    Type: Application
    Filed: August 30, 2016
    Publication date: September 14, 2017
    Inventor: Tatsuya NISHIWAKI
  • Patent number: 9660071
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a conductive layer, a gate electrode, and a first electrode. The conductive layer includes a first portion, a second portion, and a third portion. The first portion is surrounded by the first semiconductor region via a first insulating portion. The second portion extends in a second direction, is provided on the first semiconductor region, and is provided on the second region. The third portion is connected between the first portion and the second portion and extends in a third direction. The first electrode is electrically connected to the third semiconductor region and the conductive layer. The second portion electrically connects the first electrode to the third portion.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: May 23, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Katou, Tatsuya Nishiwaki, Masatoshi Arai, Hiroaki Katsuda, Chikako Yoshioka, Yoshitaka Hokomoto
  • Publication number: 20170062604
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a conductive layer, a gate electrode, and a first electrode. The conductive layer includes a first portion, a second portion, and a third portion. The first portion is surrounded by the first semiconductor region via a first insulating portion. The second portion extends in a second direction, is provided on the first semiconductor region, and is provided on the second region. The third portion is connected between the first portion and the second portion and extends in a third direction. The first electrode is electrically connected to the third semiconductor region and the conductive layer. The second portion electrically connects the first electrode to the third portion.
    Type: Application
    Filed: March 2, 2016
    Publication date: March 2, 2017
    Inventors: Hiroaki KATOU, Tatsuya NISHIWAKI, Masatoshi ARAI, Hiroaki KATSUDA, Chikako YOSHIOKA, Yoshitaka HOKOMOTO
  • Publication number: 20170040252
    Abstract: According to one embodiment, a semiconductor device comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a gate interconnect, a second insulating layer, and a first electrode. The first semiconductor region includes a first region and a second region provided around the first region. The gate interconnect is provided on the second region. The gate interconnect includes a first portion and a second portion provided around the second portion. A thickness in the first direction of the second portion is thinner than a thickness in the first direction of the first portion. A length in the second direction of the gate interconnect is longer than a length in the third direction of the gate electrode. The first electrode contacts the gate interconnect.
    Type: Application
    Filed: February 4, 2016
    Publication date: February 9, 2017
    Inventors: Tatsuya Nishiwaki, Masatoshi Arai, Hiroaki Katou, Hiroaki Katsuda, Chikako Yoshioka, Rieko Matoba
  • Patent number: 9559057
    Abstract: According to one embodiment, a semiconductor device comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a gate interconnect, a second insulating layer, and a first electrode. The first semiconductor region includes a first region and a second region provided around the first region. The gate interconnect is provided on the second region. The gate interconnect includes a first portion and a second portion provided around the second portion. A thickness in the first direction of the second portion is thinner than a thickness in the first direction of the first portion. A length in the second direction of the gate interconnect is longer than a length in the third direction of the gate electrode. The first electrode contacts the gate interconnect.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: January 31, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Nishiwaki, Masatoshi Arai, Hiroaki Katou, Hiroaki Katsuda, Chikako Yoshioka, Rieko Matoba
  • Publication number: 20160268420
    Abstract: A semiconductor device is provided including a first electrode and a first semiconductor layer of a first conductivity type connected to the first electrode. The semiconductor device further includes a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, and a second electrode provided on the third semiconductor layer. The semiconductor device further includes a third electrode disposed between the first electrode and the second electrode. The semiconductor device further includes a fourth electrode having an upper end connected to the second electrode, where the fourth electrode has a higher resistivity than the second electrode.
    Type: Application
    Filed: August 5, 2015
    Publication date: September 15, 2016
    Inventors: Masatoshi ARAI, Yoshitaka HOKOMOTO, Tatsuya NISHIWAKI
  • Patent number: 9379216
    Abstract: According to an embodiment, a method for manufacturing a semiconductor device includes forming a gate trench extending into a first semiconductor layer; forming a gate insulating film on an internal wall of the gate trench; forming a polysilicon in the gate trench; etching the polysilicon into the gate trench; forming an interlayer insulating film on the polysilicon; etching the first semiconductor layer so as to project the interlayer insulating film from the first semiconductor layer; forming a second semiconductor layer on the first semiconductor layer; forming a third semiconductor layer on the second semiconductor layer; forming a sidewall contacting a side face of the interlayer insulating film; forming a fourth semiconductor layer of the second conductivity type in the second semiconductor layer; and forming a first electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: June 28, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Nishiwaki, Yoshitaka Hokomoto, Masatoshi Arai
  • Publication number: 20150364562
    Abstract: A semiconductor device includes a first semiconductor layer that includes a first region and a second region, a second semiconductor layer that is provided on an upper side of the first semiconductor layer, a third semiconductor layer that is selectively provided on an upper side of the second semiconductor layer, a control electrode provided in the second semiconductor layer and the third semiconductor layer through an insulation film, a first conductor that is provided in the first semiconductor layer so as to be in contact with the control electrode and the first semiconductor layer through the insulation film and is positioned further on a first semiconductor layer side than the control electrode, a second conductor that extends in a direction from the third semiconductor layer to the first semiconductor layer in the second region and is provided in the first semiconductor layer through an insulation film, a first electrode that is electrically connected to the first semiconductor layer, the second semico
    Type: Application
    Filed: March 6, 2015
    Publication date: December 17, 2015
    Inventors: Yoshitaka Hokomoto, Tatsuya Nishiwaki, Masatoshi Arai
  • Publication number: 20150207407
    Abstract: According to one embodiment, in semiconductor device, first semiconductor region is provided between first electrode and second electrode. Second semiconductor region is provided between first semiconductor region and second electrode. Third semiconductor region is provided between second semiconductor region and second electrode. Third electrode is in contact with first semiconductor region, second semiconductor region, and third semiconductor region via insulating film. Element part is configured to detect heat released from at least one of first semiconductor region, second semiconductor region, and third semiconductor region. Fourth semiconductor region is provided between first semiconductor region and second electrode. Fifth semiconductor region is provided between fourth semiconductor region and second electrode. And fourth electrode is in contact with first semiconductor region, fourth semiconductor region, and fifth semiconductor region via insulating film.
    Type: Application
    Filed: July 9, 2014
    Publication date: July 23, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuya Nishiwaki