Patents by Inventor Te-An Chen

Te-An Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • COMBINATION THERAPIES COMPRISING APREMILAST AND TYK2 INHIBITORS
    Publication number: 20220339151
    Abstract: Provided herein are methods of treating diseases and disorder responsive to the inhibition of PDE4 comprising administering apremilast and a Tyk2 inhibitor to a subject. Also provided herein are pharmaceutical compositions comprising apremilast and a Tyk2 inhibitor.
    Type: Application
    Filed: May 9, 2022
    Publication date: October 27, 2022
    Inventors: Peter Henry Schafer, Robert Plenge, Mary Adams, Lisa Beebe, Gilles Buchwalter, Tiffany Carr, Te-chen Tzeng
  • METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND A SEMICONDUCTOR DEVICE
    Publication number: 20220336286
    Abstract: In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Te-An CHEN, Meng-Han LIN
  • SEMICONDUCTOR DEVICE AND METHODS OF FORMING THE SAME
    Publication number: 20220328472
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a first gate structure disposed on the substrate within the first region, a first S/D region, a first S/D contact, a second gate structure on the substrate within the second region, a second S/D region and a second S/D contact. The first S/D region is disposed in the substrate within the first region and beside the first gate structure. The first S/D contact is connected to the first S/D region. The second S/D region is disposed in the substrate within the second region and beside the second gate structure. The second S/D contact is connected to the second S/D region. The contact area between the second S/D region and the second S/D contact is larger than a contact area between the first S/D region and the first S/D contact.
    Type: Application
    Filed: June 20, 2022
    Publication date: October 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Te-An Chen
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20220320130
    Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.
    Type: Application
    Filed: June 6, 2022
    Publication date: October 6, 2022
    Inventors: Meng-Han LIN, Te-An CHEN
  • SEMICONDUCTOR DEVICE STRUCTURE WITH RESISTIVE ELEMENT
    Publication number: 20220319987
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.
    Type: Application
    Filed: June 23, 2022
    Publication date: October 6, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Te CHEN, Chung-Hui CHEN, Wei-Chih CHEN, Chii-Ping CHEN, Wen-Sheh HUANG, Bi-Ling LIN, Sheng-Feng LIU
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME
    Publication number: 20220320319
    Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.
    Type: Application
    Filed: August 10, 2021
    Publication date: October 6, 2022
    Inventors: MING-TE CHEN, HUI-TING TSAI, JUN HE, KUO-FENG YU, CHUN HSIUNG TSAI
  • CAPACITOR AND METHOD FOR FORMING THE SAME
    Publication number: 20220302019
    Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a bottom electrode routing, a capacitor structure, a top electrode routing. The bottom electrode routing is over the semiconductor substrate. The capacitor structure is over the bottom electrode routing. The capacitor structure includes a bottom metal layer, a middle metal layer above the bottom metal layer, and a top metal layer above the middle metal layer. When viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction.
    Type: Application
    Filed: July 9, 2021
    Publication date: September 22, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Te CHEN, Chung-Hui CHEN, Wei Chih CHEN
  • Sensing device and sensing system for human-powered devices using the same
    Patent number: 11448662
    Abstract: A sensing device has a strain gauge device, an idler, and a connecting rod assembly. The sensing device receives a mechanical force to generate a deformation accordingly, and generates a sensing signal according to the deformation. The idler is a ring body which has a ring contracting portion contacting a transmission belt, so as to receive the mechanical force which the transmission belt applies on the idler. A first end of the connecting rod assembly is connected to the strain gauge device via a rod slot which is located on a side of the strain gauge device, and a second end of the connecting rod assembly is pivotally connected to the idler via a pivot connecting portion of the idler, such that the mechanical force which the idler suffers can be transmitted to the strain gauge device.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: September 20, 2022
    Inventor: Tsu-Te Chen
  • Semiconductor device and method of fabricating the same
    Patent number: 11450660
    Abstract: Provided is a semiconductor device including a substrate, an isolation structure, a gate dielectric layer, a high-k dielectric layer, and a protection cap. The substrate includes a first region, a second region, and a transition region located between the first region and the second region. The isolation structure, located in the transition region. The gate dielectric layer is located on the isolation structure. The high-k dielectric layer is located on the isolation structure and extended to cover a sidewall and a surface of the gate dielectric layer. The protection cap is located on a surface and sidewalls of the high-k dielectric layer.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Te-An Chen
  • SCHOTTKY BARRIER DIODE WITH REDUCED LEAKAGE CURRENT AND METHOD OF FORMING THE SAME
    Publication number: 20220285524
    Abstract: A semiconductor device includes a first well region in a substrate; a first dielectric layer over the first well region, wherein the first dielectric layer includes a stepped shape over the first well region; and a conductive layer over the first well region. The conductive layer forms a Schottky barrier interface with the first well region.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Inventors: MENG-HAN LIN, TE-AN CHEN
  • SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
    Publication number: 20220285496
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate including a well region and an adjustment region over the well region. An isolation structure is disposed over the substrate and at least partially surrounds the well region and the adjustment region. An epitaxial layer is disposed over the adjustment region and surrounded by the isolation structure. A gate structure is disposed on the epitaxial layer. The present disclosure also provides a method for forming a semiconductor structure.
    Type: Application
    Filed: March 4, 2021
    Publication date: September 8, 2022
    Inventors: TE-AN CHEN, MENG-HAN LIN
  • CIRCUITS DESIGNED AND MANUFACTURED WITH FIRST AND SECOND DESIGN RULES
    Publication number: 20220278099
    Abstract: An integrated circuit (IC) including a plurality of finfet cells designed with digital circuit design rules to provide smaller finfet cells with decreased cell heights, and analog circuit cell structures including first finfet cells of the plurality of finfet cells and including at least one cut metal layer. The smaller finfet cells with decreased cell heights provide a first shorter metal track in one direction and the at least one cut metal layer provides a second shorter metal track in another direction to increase maximum electromigration currents in the integrated circuit.
    Type: Application
    Filed: December 3, 2021
    Publication date: September 1, 2022
    Inventors: Chung-Hui Chen, Tzu-Ching Chang, Weichih Chen, Wan-Te Chen, Tsung-Hsin Yu, Cheng-Hsiang Hsieh
  • CAPACITOR IN NANOSHEET
    Publication number: 20220278093
    Abstract: A semiconductor device includes a substrate. A first nanosheet structure and a second nanosheet structure are disposed on the substrate. Each of the first and second nanosheet structures have at least one nanosheet forming source/drain regions and a gate structure including a conductive gate contact. A first oxide structure is disposed on the substrate between the first and second nanosheet structures. A conductive terminal is disposed in or on the first oxide structure. The conductive terminal, the first oxide structure and the gate structure of the first nanosheet structure define a capacitor.
    Type: Application
    Filed: December 10, 2021
    Publication date: September 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hui CHEN, Wan-Te CHEN, Shu-Wei CHUNG, Tung-Heng HSIEH, Tzu-Ching CHANG, Tsung-Hsin YU, Yung Feng CHANG
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20220278092
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a first active region extending along a first direction. The semiconductor device also includes a second active region extending along the first direction. The semiconductor device further includes a first gate extending along a second direction perpendicular to the first direction. The first gate has a first segment disposed between the first active region and the second active region. In addition, the semiconductor device includes a first electrical conductor extending along the second direction and across the first active region and the second active region, wherein the first segment of the first gate and the first electrical conductor are partially overlapped to form a first capacitor.
    Type: Application
    Filed: June 24, 2021
    Publication date: September 1, 2022
    Inventors: CHUNG-HUI CHEN, WAN-TE CHEN, TZU CHING CHANG, TSUNG-HSIN YU
  • Verified Participant Database System for Surveys and Promotions
    Publication number: 20220253885
    Abstract: In general, the subject matter described in the specification can be embodied in methods, systems and program products for a verified participant database system that verifies information on potential participants for surveys and promotions that require numerous participants with certain characteristics. Among other features, the verified participant database system aggregates and preferably verifies information, for example, the demographic and purchasing information, of potential participants by receiving permission to obtain information from third-party sources.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 11, 2022
    Inventor: Philip Ta-te CHEN
  • Semiconductor device structure with resistive element
    Patent number: 11404369
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. The thermal conductive element at least partially overlaps the resistive element. In addition, the semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Te Chen, Chung-Hui Chen, Wei-Chih Chen, Chii-Ping Chen, Wen-Sheh Huang, Bi-Ling Lin, Sheng-Feng Liu
  • Semiconductor device having different voltage regions
    Patent number: 11404410
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a first gate structure disposed on the substrate within the first region, a first S/D region, a first S/D contact, a second gate structure on the substrate within the second region, a second S/D region and a second S/D contact. The first S/D region is disposed in the substrate within the first region and beside the first gate structure. The first S/D contact is connected to the first S/D region. The second S/D region is disposed in the substrate within the second region and beside the second gate structure. The second S/D contact is connected to the second S/D region. The contact area between the second S/D region and the second S/D contact is larger than a contact area between the first S/D region and the first S/D contact.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Te-An Chen
  • ELECTRONIC DEVICE
    Publication number: 20220238477
    Abstract: An electronic device includes a substrate, a plurality of micro semiconductor structure, a plurality of conductive members, and a non-conductive portion. The substrate has a first surface and a second surface opposite to each other. The micro semiconductor structures are distributed on the first surface of the substrate. The conductive members electrically connect the micro semiconductor structures to the substrate. Each conductive member is defined by an electrode of one of the micro semiconductor structures and a corresponding conductive pad on the substrate. The non-conductive portion is arranged on the first surface of the substrate. The non-conductive portion includes one or more non-conductive members, and the one or more non-conductive members are attached to the corresponding one or more conductive members of the one or more micro conductive structures.
    Type: Application
    Filed: January 25, 2022
    Publication date: July 28, 2022
    Inventor: HSIEN-TE CHEN
  • PROJECTION LENS
    Publication number: 20220229268
    Abstract: The disclosure provides a projection lens including a first lens set and a second lens set disposed sequentially from a magnified side to a reduced side. The first lens set and the second lens set are separated by a minimum inner diameter of a lens barrel. The first lens set includes 4 to 6 spherical lenses, and a refractive power of the first lens set is negative. The second lens set includes 4 to 6 lenses, where one of the lenses is an aspheric lens, and a refractive power of the second lens set is positive. A transmittance of the projection lens at a wavelength of 365 nm is greater than or equal to 75%.
    Type: Application
    Filed: January 17, 2022
    Publication date: July 21, 2022
    Applicant: Young Optics Inc.
    Inventors: Shuo-Chieh Chang, Ching-Lung Lai, Hsin-Te Chen, Kuo-Chuan Wang
  • Combination therapies comprising apremilast and Tyk2 inhibitors
    Patent number: 11357775
    Abstract: Provided herein are methods of treating diseases and disorder responsive to the inhibition of PDE4 comprising administering apremilast and a Tyk2 inhibitor to a subject. Also provided herein are pharmaceutical compositions comprising apremilast and a Tyk2 inhibitor.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: June 14, 2022
    Assignee: Celgene Corporation
    Inventors: Peter Henry Schafer, Robert Plenge, Mary Adams, Lisa Beebe, Gilles Buchwalter, Tiffany Carr, Te-chen Tzeng