Abstract: A method of manufacturing a Schottky barrier diode includes: forming a first well region over a substrate; forming a first dielectric layer over the first well region; patterning the first dielectric layer by reducing a first thickness of the first dielectric layer; removing the first dielectric layer to expose a surface of the first well region; and forming a conductive layer over the first well region to obtain a Schottky barrier interface. A Schottky barrier diode manufactured based on the above method is also provided.

Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a first cyclic redundancy check (CRC) circuit, a second CRC circuit, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The interface circuit receives and provides a first data portion of the decoded codeword to a host. The first CRC circuit performs a first CRC on the first data portion and generates a check status message based on a relationship between a result of the first CRC and a first CRC code of the decoded codeword. The second CRC circuit performs a second CRC on the first data portion to generate a second CRC code. The second CRC circuit determines whether to further change the second CRC code to make the second CRC code not match the first data portion according to the check status message.

Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top fin surface, an upper fin side surface portion adjacent to the top fin surface, and a lower fin side surface contiguously connected to the upper fin side surface portion. The lining oxide layer peripherally encloses the lower fin side surface portion of the semiconductor fin. The silicon nitride based layer is disposed conformally over the lining oxide layer. The gate oxide layer is disposed conformally over the top fin surface and the upper fin side surface portion.

Abstract: A driving method for a liquid crystal display device is provided. The liquid crystal display device has a wide viewing angle mode and a narrow viewing angle mode. The driving method includes: in the wide viewing angle mode, all the frames of the liquid crystal display device have the same display brightness; in the narrow viewing angle mode, the odd frames and the even frames of the liquid crystal display device have different display brightness. In the narrow viewing angle mode of the liquid crystal display device, by using an alternate driving method of bright frames and dark frames, the mura degree is significantly reduced, and the smoothness of dynamic picture display is improved, thereby improving the use experience of users.

Abstract: A micro semiconductor stacked structure includes at least two stacked structure array units, wherein one stacked structure array unit is stacked on the other stacked structure array unit. In particular, the stacked structure array unit is stacked on the other stacked structure array unit along a vertical direction. Each stacked structure array unit includes a substrate, a conductive pattern layer disposed on the substrate, and a plurality of micro semiconductor devices disposed on the substrate and electrically connected to the conductive pattern layer.

Abstract: A capacitor structure including a semiconductor substrate; a dielectric layer on the semiconductor substrate; a storage node pad in the dielectric layer; a lower electrode including a bottle-shaped bottom portion recessed into the dielectric layer and being in direct contact with the storage node pad; and a lattice layer supporting a topmost part of the lower electrode, wherein the lattice layer is not directly contacting the dielectric layer, but is directly contacting the topmost part of the lower electrode. The bottle-shaped bottom portion extends to a sidewall of the storage node pad. The bottle-shaped bottom portion has a width that is wider than other portion of the lower electrode.

Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.

Abstract: A viewing angle switchable liquid crystal display device includes a display panel. The display panel includes a first substrate, a second substrate disposed opposite the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. The second substrate is provided with a first electrode and a second electrode. The first electrode is a common electrode, and the second electrode is a pixel electrode. The first substrate is provided with a third electrode for controlling the switching of the viewing angle. A periodic alternating voltage is applied to the third electrode when the viewing angle of the liquid crystal display device is switched, and a period of the periodic alternating voltage is an even multiple of a refresh period of each frame of the display panel.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

Abstract: An optical lens includes a first lens group, a second lens group and an aperture stop disposed between the first lens group and the second lens group. The optical lens satisfies the conditions of 7 mm<D<25 mm and 0.3<D/LT<0.5, where D is a diameter of a lens surface of the second lens group furthest from the first lens group and LT is a total lens length measured along an optical axis between a lens surface of the first lens group furthest from the second lens group and the lens surface of the second lens group furthest from the first lens group.

Abstract: A semiconductor device includes a substrate, a metal gate and a poly gate. The substrate includes a first region and a second region. The metal gate is disposed on the first region of the substrate. The poly gate is disposed on the second region of the substrate. A gate area of the poly gate is greater than that of the metal gate.

Abstract: A semiconductor device includes a gate structure disposed over a channel region, a source/drain epitaxial layer disposed at a source/drain region, a nitrogen containing layer disposed on the source/drain epitaxial layer, a silicide layer disposed on the nitrogen containing layer, and a conductive contact disposed on the silicide layer.

Abstract: An intelligent fan control system with interface compatibility is provided. The intelligent fan control system can identify and control fans one-to-one connected to fan slots, and each fan slot includes four pins. The intelligent fan control system includes a bus; an I2C signal switching unit including SDA outputs one-to-one connected to third pin of the fan slots via the bus; an I2C signal switching unit including SCL outputs one-to-one connected to fourth pins of the fan slots via the bus; voltage control units one-to-one corresponding to the fan slots, and having output terminals one-to-one connected to second pins of the fan slots; connection line sets, and each connection line set including four connection lines and connected to the corresponding fan slot; a control board comprising port sets, and can control and switch the I2C signal switching unit to the fan slots in sequence, to transmit the corresponding I2C signal.

Abstract: A bumped solder pad and methods for adding bumps to a solder pad are provided. A substrate is provided having metal layer formed thereon and a solder pad formed from a portion of the metal layer. A surface treatment is applied to the solder pad. The surface treatment is patterned. The surface treatment is etched to produce at least one bump on the solder pad.

Abstract: A method of manufacturing a semiconductor device based on a dual-architecture-compatible design includes: forming transistor components of in a transistor (TR) layer; and performing one of fabricating additional components according to (A) a buried power rail (BPR) type of architecture or (B) a non-buried power rail (non-BPR) type of architecture. The step (A) includes, in corresponding sub-TR layers, forming various non-dummy sub-TR structures, and, in corresponding supra-TR layers, forming various dummy supra-TR structures which are corresponding first artifacts. The step (B) includes, in corresponding supra-TR layers, forming various non-dummy supra-TR structures and forming various dummy supra-TR structures which are corresponding second artifacts, the first and second artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the BPR type of architecture.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A touch display panel with switchable viewing angles includes a first substrate, a second substrate, and a liquid crystal layer between the first substrate and the second substrate. The first substrate is provided with a viewing angle control electrode. The second substrate is provided with a common electrode and a sensing circuit layer. The common electrode includes a plurality of electrode blocks arranged in an array and insulated from each other. The sensing circuit layer includes a plurality of sensing lines insulated from each other. The sensing lines are electrically connected to the electrode blocks in a one-to-one correspondence, respectively. Each frame of the display panel is divided into a display period and a touch period. The electrode blocks of the common electrode are used for image display during the display period, and the electrode blocks of the common electrode are used for touch sensing during the touch period.

Abstract: A method for driving a liquid crystal display device capable of switching between a wide viewing angle and a narrow viewing angle. In a first viewing angle mode, a direct-current common voltage is applied to a common electrode and voltage signals are applied to a first bias electrode and a second bias electrode. In a second viewing angle mode, a direct-current common voltage is applied to the common electrode, a first alternating-current voltage is applied to the first bias electrode and a second alternating-current voltage is applied to the second bias electrode. In addition, in the second viewing angle mode, pixel units covered by each first electrode strip of the first bias electrode have alternating positive and negative polarities, and pixel units covered by each second electrode strip of the second bias electrode have alternating positive and negative polarities.

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.