Abstract: A memory device includes an alternating stack of dielectric layers and word line layers, pairs of bit lines and source lines spaced apart from one another, a data storage layer covering a sidewall of the alternating stack, and channel layers interposed between the data storage layer and the pairs of bit lines and source lines. The alternating stack includes a staircase structure in a staircase-shaped region, and the staircase structure steps downward from a first direction and includes at least one turn. The pairs of bit lines and source lines extend in a second direction that is substantially perpendicular to the first direction and are in lateral contact with the data storage layer through the channel layers. A semiconductor structure and a method are also provided.

Abstract: A semiconductor device includes a transistor. The transistor includes a gate electrode, a channel layer, a gate dielectric layer, a first source/drain region and a second source/drain region and a dielectric pattern. The channel layer is disposed on the gate electrode. The gate dielectric layer is located between the channel layer and the gate electrode. The first source/drain region and the second source/drain region are disposed on the channel layer at opposite sides of the gate electrode. The dielectric pattern is disposed on the channel layer. The first source/drain region covers a first sidewall and a first surface of the dielectric pattern, and a second sidewall opposite to the first sidewall of the dielectric pattern is protruded from a sidewall of the first source/drain region.

Abstract: A method of forming a semiconductor structure includes following operations. A memory layer is formed over the first gate electrode. A channel layer is formed over the memory layer. A first SUT treatment is performed. A second dielectric layer is formed over the memory layer and the channel layer. A source electrode and a drain electrode are formed in the second dielectric layer. A temperature of the first SUT treatment is less than approximately 400° C.

Abstract: A semiconductor device includes a semiconductor substrate and an interconnection region disposed on the semiconductor substrate. The interconnection region includes stacked metallization levels, a magnetic tunnel junction, and a transistor. The magnetic tunnel junction is formed on a first conductive pattern of a first metallization level of the stacked metallization levels. The transistor is formed on a second conductive pattern of a second metallization level of the stacked metallization levels. The transistor is a vertical gate-all-around transistor. A drain contact of the transistor is electrically connected to the magnetic tunnel junction by the first conductive pattern of the first metallization level. The second metallization level is closer to the semiconductor substrate than the first metallization level.

Abstract: A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

Abstract: A semiconductor device includes a transistor. The transistor includes a gate electrode, a channel layer, a gate dielectric layer, a first source/drain region and a second source/drain region and a first spacer. The channel layer is disposed on the gate electrode. The gate dielectric layer is located between the channel layer and the gate electrode. The first source/drain region and the second source/drain region are disposed on the channel layer at opposite sides of the gate electrode, and at least one of the first and second source/drain regions includes a first portion and a second portion between the first portion and the gate electrode. The first spacer is disposed on the channel layer. The first spacer is disposed on a first sidewall of the second portion of the at least one of the first and second source/drain regions, and the first portion is disposed on the first spacer.

Abstract: In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.

Abstract: A semiconductor arrangement and method of manufacture is provided. In some embodiments, a semiconductor arrangement includes a collector region having a first surface coplanar with a first surface of a semiconductor layer, a drift region over a portion of the collector region and having a first surface coplanar with the first surface of the semiconductor layer, and a body region over the drift region. A body contact is in the body region. An emitter contact contacts the body contact and the body region. A collector contact contacts the first surface of the collector region. A first gate structure is adjacent the first surface of the drift region, the body region, and the body contact.

Abstract: The present disclosure describes a semiconductor device with substantially uniform gate regions and a method for forming the same. The method includes forming a fin structure on a substrate, the fin structure including one or more nanostructures. The method further includes removing a portion of the fin structure to expose an end of the one or more nanostructures and etching the end of the one or more nanostructures with one or more etching cycles. Each etching cycle includes purging the fin structure with hydrogen fluoride (HF), etching the end of the one or more nanostructures with a gas mixture of fluorine (F2) and HF, and removing an exhaust gas mixture including an etching byproduct. The method further includes forming an inner spacer in the etched end of the one or more nanostructures.

Abstract: A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.

Abstract: A semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate. The transistor array includes unit cells and spacers. The unit cells are disposed along rows of the transistor array extending in a first direction and columns of the transistor array extending in a second direction perpendicular to the first direction. The spacers encircle the unit cells. The unit cells include source contacts and drain contacts separated by interlayer dielectric material portions. First sections of the spacers contacting the interlayer dielectric material portions are thicker than second sections of the spacers contacting the source contacts and the drain contacts.

Abstract: A semiconductor device includes a transistor. The transistor includes a gate electrode, a channel layer, a gate dielectric layer, a first source/drain region and a second source/drain region and a dielectric pattern. The channel layer is disposed on the gate electrode. The gate dielectric layer is located between the channel layer and the gate electrode. The first source/drain region and the second source/drain region are disposed on the channel layer at opposite sides of the gate electrode. The dielectric pattern is disposed on the channel layer. The first source/drain region covers a first sidewall and a first surface of the dielectric pattern, and a second sidewall opposite to the first sidewall of the dielectric pattern is protruded from a sidewall of the first source/drain region.

Abstract: A method for profit sharing is provided. The method includes deciding a first sharing rate according to a first event information and a first category information; obtaining a first sharing amount according to the first sharing rate and a first shared profit of the first category information; deciding a second sharing rate according to a second event information and a second category information; obtaining a second sharing amount according to the second sharing rate and a second shared profit of the second category information; deciding a total sharing amount by summing up the first sharing amount and the second sharing amount; and returning the total sharing amount in response to receiving a request from a user device.

Abstract: The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.

Abstract: A processing apparatus is provided. The processing apparatus includes a chamber and a carrier that is positioned in the chamber for holding a substrate. The processing apparatus further includes a gas inlet connected to the chamber. The gas inlet is configured to supply a process gas into the chamber. The processing apparatus also includes a coil module positioned around the chamber and configured to transfer the process gas into plasma. In addition, the processing apparatus includes a filter disposed in the chamber. The coil module is configured to change a position of the plasma between a first position and a second position, the first position is located between the gas inlet and the filter, and the second position is located between the filter and the carrier.

Abstract: A disclosed high-density capacitor includes a top electrode having an electrically conducting material forming a three-dimensional structure. The three-dimensional structure includes a plurality of vertical portions extending in a vertical direction and horizontal portions, that are interleaved within the vertical portions and extend in a first horizontal direction. The high-density capacitor further includes a dielectric layer formed over the top electrode, and a bottom electrode including an electrically conducting material, such that the bottom electrode is separated from the top electrode by the dielectric layer. Further, the bottom electrode envelopes some of the plurality of vertical portions of the top electrode. The disclosed high-density capacitor further includes a plurality of support structures that are aligned with the first horizontal direction such that the horizontal portions of the top electrode are formed under respective support structures.

Abstract: A semiconductor structure includes a semiconductor substrate, a metal layer, an interlayer dielectric (ILD) layer. The metal layer is disposed over the semiconductor substrate. The ILD layer is over the semiconductor substrate and laterally surrounding the metal layer, in which the ILD layer has a first portion in contact with a first sidewall of the metal layer and a second portion in contact with a second sidewall of the metal layer opposite to the first sidewall of the metal layer, and a width of the first portion of the ILD layer decreases as a distance from the semiconductor substrate increases.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

Abstract: Some embodiments relate to a memory device. The memory device includes a substrate comprising an inter-metal dielectric layer having a metal line, a dielectric layer over the substrate, a bottom electrode via through the dielectric layer and in contact with the metal line, a bottom electrode over the bottom electrode via, a magnetic tunneling junction (MTJ) element over the bottom electrode, and a top electrode over the MTJ element. A center portion of the bottom electrode directly above the bottom electrode via is thicker than an edge portion of the bottom electrode.

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.