Patents by Inventor Te-An Lin

Te-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230027039
    Abstract: In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.
    Type: Application
    Filed: August 10, 2022
    Publication date: January 26, 2023
    Inventors: Chia Yu Ling, Chung-Te Lin, Katherine H. Chiang
  • Publication number: 20230028453
    Abstract: A semiconductor arrangement and method of manufacture is provided. In some embodiments, a semiconductor arrangement includes a collector region having a first surface coplanar with a first surface of a semiconductor layer, a drift region over a portion of the collector region and having a first surface coplanar with the first surface of the semiconductor layer, and a body region over the drift region. A body contact is in the body region. An emitter contact contacts the body contact and the body region. A collector contact contacts the first surface of the collector region. A first gate structure is adjacent the first surface of the drift region, the body region, and the body contact.
    Type: Application
    Filed: March 14, 2022
    Publication date: January 26, 2023
    Inventor: Hung-Te LIN
  • Publication number: 20230027676
    Abstract: The present disclosure describes a semiconductor device with substantially uniform gate regions and a method for forming the same. The method includes forming a fin structure on a substrate, the fin structure including one or more nanostructures. The method further includes removing a portion of the fin structure to expose an end of the one or more nanostructures and etching the end of the one or more nanostructures with one or more etching cycles. Each etching cycle includes purging the fin structure with hydrogen fluoride (HF), etching the end of the one or more nanostructures with a gas mixture of fluorine (F2) and HF, and removing an exhaust gas mixture including an etching byproduct. The method further includes forming an inner spacer in the etched end of the one or more nanostructures.
    Type: Application
    Filed: March 8, 2022
    Publication date: January 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Chien Kuang, Wei-Lun Chen, Tze-Chung Lin, Li-Te Lin
  • Publication number: 20230024339
    Abstract: A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.
    Type: Application
    Filed: February 9, 2022
    Publication date: January 26, 2023
    Inventors: Chih-Hsuan Cheng, Chieh-Fang Chen, Sheng-Chen Wang, Chieh-Yi Shen, Han-Jong Chia, Feng-Ching Chu, Meng-Han Lin, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20230028561
    Abstract: A semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate. The transistor array includes unit cells and spacers. The unit cells are disposed along rows of the transistor array extending in a first direction and columns of the transistor array extending in a second direction perpendicular to the first direction. The spacers encircle the unit cells. The unit cells include source contacts and drain contacts separated by interlayer dielectric material portions. First sections of the spacers contacting the interlayer dielectric material portions are thicker than second sections of the spacers contacting the source contacts and the drain contacts.
    Type: Application
    Filed: July 23, 2021
    Publication date: January 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gao-Ming Wu, Katherine H. CHIANG, Chien-Hao Huang, Chung-Te Lin
  • Publication number: 20230022020
    Abstract: A semiconductor device includes a transistor. The transistor includes a gate electrode, a channel layer, a gate dielectric layer, a first source/drain region and a second source/drain region and a dielectric pattern. The channel layer is disposed on the gate electrode. The gate dielectric layer is located between the channel layer and the gate electrode. The first source/drain region and the second source/drain region are disposed on the channel layer at opposite sides of the gate electrode. The dielectric pattern is disposed on the channel layer. The first source/drain region covers a first sidewall and a first surface of the dielectric pattern, and a second sidewall opposite to the first sidewall of the dielectric pattern is protruded from a sidewall of the first source/drain region.
    Type: Application
    Filed: July 23, 2021
    Publication date: January 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Feng Yin, Chia-Jung Yu, Pin-Cheng Hsu, Chung-Te Lin
  • Patent number: 11562403
    Abstract: A method for profit sharing is provided. The method includes deciding a first sharing rate according to a first event information and a first category information; obtaining a first sharing amount according to the first sharing rate and a first shared profit of the first category information; deciding a second sharing rate according to a second event information and a second category information; obtaining a second sharing amount according to the second sharing rate and a second shared profit of the second category information; deciding a total sharing amount by summing up the first sharing amount and the second sharing amount; and returning the total sharing amount in response to receiving a request from a user device.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: January 24, 2023
    Assignee: OBOOK INC.
    Inventors: Chun-Kai Wang, Chung-Han Hsieh, Hsiu-An Teng, Chih-Yang Liu, Wei-Te Lin, I-Cheng Lin, Shin-Ying Chu, Zih-Hao Lin, Kang-Hsien Chang
  • Publication number: 20230017512
    Abstract: The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tze-Chung LIN, Pinyen LIN, Fang-Wei LEE, Li-Te LIN, Han-yu LIN
  • Publication number: 20230018022
    Abstract: A processing apparatus is provided. The processing apparatus includes a chamber and a carrier that is positioned in the chamber for holding a substrate. The processing apparatus further includes a gas inlet connected to the chamber. The gas inlet is configured to supply a process gas into the chamber. The processing apparatus also includes a coil module positioned around the chamber and configured to transfer the process gas into plasma. In addition, the processing apparatus includes a filter disposed in the chamber. The coil module is configured to change a position of the plasma between a first position and a second position, the first position is located between the gas inlet and the filter, and the second position is located between the filter and the carrier.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 19, 2023
    Inventors: Yu-Rung HSU, Li-Te LIN, Pinyen LIN
  • Publication number: 20230011756
    Abstract: A disclosed high-density capacitor includes a top electrode having an electrically conducting material forming a three-dimensional structure. The three-dimensional structure includes a plurality of vertical portions extending in a vertical direction and horizontal portions, that are interleaved within the vertical portions and extend in a first horizontal direction. The high-density capacitor further includes a dielectric layer formed over the top electrode, and a bottom electrode including an electrically conducting material, such that the bottom electrode is separated from the top electrode by the dielectric layer. Further, the bottom electrode envelopes some of the plurality of vertical portions of the top electrode. The disclosed high-density capacitor further includes a plurality of support structures that are aligned with the first horizontal direction such that the horizontal portions of the top electrode are formed under respective support structures.
    Type: Application
    Filed: March 10, 2022
    Publication date: January 12, 2023
    Inventors: Cheng-Yi WU, Katherine H. CHIANG, Chung-Te LIN, Hsin-Yu LAI, Yun-Feng KAO
  • Patent number: 11551966
    Abstract: A semiconductor structure includes a semiconductor substrate, a metal layer, an interlayer dielectric (ILD) layer. The metal layer is disposed over the semiconductor substrate. The ILD layer is over the semiconductor substrate and laterally surrounding the metal layer, in which the ILD layer has a first portion in contact with a first sidewall of the metal layer and a second portion in contact with a second sidewall of the metal layer opposite to the first sidewall of the metal layer, and a width of the first portion of the ILD layer decreases as a distance from the semiconductor substrate increases.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Shan Chen, Chan-Syun David Yang, Li-Te Lin, Pinyen Lin
  • Patent number: 11545397
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu Lin, Jhih-Rong Huang, Yen-Tien Tung, Tzer-Min Shen, Fu-Ting Yen, Gary Chan, Keng-Chu Lin, Li-Te Lin, Pinyen Lin
  • Publication number: 20220406992
    Abstract: Some embodiments relate to a memory device. The memory device includes a substrate comprising an inter-metal dielectric layer having a metal line, a dielectric layer over the substrate, a bottom electrode via through the dielectric layer and in contact with the metal line, a bottom electrode over the bottom electrode via, a magnetic tunneling junction (MTJ) element over the bottom electrode, and a top electrode over the MTJ element. A center portion of the bottom electrode directly above the bottom electrode via is thicker than an edge portion of the bottom electrode.
    Type: Application
    Filed: April 21, 2022
    Publication date: December 22, 2022
    Inventors: Yi-Cheng Chu, Chung-Te Lin, Kai-Wen Cheng, Han-Ting Tsai, Jung-Tsan Tsai, Pao-Yi Tai, Chien-Hua Huang
  • Patent number: 11532640
    Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Jong Chia, Chung-Te Lin, Feng-Cheng Yang, Meng-Han Lin, Sheng-Chen Wang
  • Publication number: 20220398582
    Abstract: An information delivery method for transferring fund is provided. The information delivery method includes receiving payment information, determining whether a transfer condition is met according to the payment information, in response to determining that the transfer condition is met, obtaining source account information of a source entity and destination account information of a destination entity in the payment information, determining a transfer path according to the source account information of the source entity and the destination account information of the destination entity, and transmitting the payment information from the source entity to the destination entity according to the transfer path.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 15, 2022
    Applicant: OBOOK INC.
    Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chih-Yang Liu, Wei-Te Lin, I-Cheng Lin, Jun-De Liao, Kang-Hsien Chang, Chun-Jen Chen, Pei-Hsuan Weng, Yi-Hsuan Lai, Ming-Hung Lin, Shu-Ming Chang, Zih-Hao Lin
  • Publication number: 20220397352
    Abstract: graphite composite laminated heat-dissipating structure and a manufacturing method thereof are disclosed. The structure includes a metal substrate and a graphite heat-dissipating layer. The metal substrate has a first surface having a roughness ranging between 0.01 and 10 ?m. The graphite heat-dissipating layer is composed of pure graphite and is directly formed on the first surface by means of physical vapor deposition using a carbon sputtering target. The graphite heat-dissipating layer has a thickness ranging between 0.05 and 2 ?m. The manufacturing method includes S1: directly forming a graphite heat-dissipating layer on a first surface of a metal substrate by means of physical vapor deposition using a carbon sputtering target after the metal substrate has received plasma treatment or infrared heating; and S2: stopping the physical vapor deposition when the graphite heat-dissipating layer has a thickness ranging between 0.05 and 2 ?m.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 15, 2022
    Inventors: KUO-CHEN HSU, CHIA-YANG KUO, CHIEN-HAO SU, CHAO-TE LIN
  • Patent number: 11527649
    Abstract: Ferroelectric structures, including a ferroelectric field effect transistors (FeFETs), and methods of making the same are disclosed which have improved ferroelectric properties and device performance. A FeFET device including a ferroelectric material gate dielectric layer and a metal oxide semiconductor channel layer is disclosed having improved ferroelectric characteristics, such as increased remnant polarization, low defects, and increased carrier mobility for improved device performance.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yen-Chieh Huang, Po-Ting Lin, Hai-Ching Chen, Song-Fu Liao, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11527553
    Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11522065
    Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Lo, Jung-Hao Chang, Li-Te Lin, Pinyen Lin
  • Publication number: 20220384460
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.
    Type: Application
    Filed: August 5, 2022
    Publication date: December 1, 2022
    Inventors: Song-Fu Liao, Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin