Patents by Inventor Tei TO

Tei TO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cathode active material containing magnesium-transition metal composite oxide and magnesium secondary battery using the same
    Patent number: 11018330
    Abstract: A cathode active material for magnesium secondary batteries contains a composite oxide represented by the formula MgxMyO2, where M is at least one selected from the group consisting of Ni, Co, Mn, Ti, V, Cr, Fe, Cu, and Mo; 1.0<x, and y<1.0.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: May 25, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Toshiro Kume, Go Tei
  • SEMICONDUCTOR STRUCTURE WITH SOURCE/DRAIN MULTI-LAYER STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20210143278
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The S/D epitaxial layer includes a first S/D epitaxial layer and a second epitaxial layer. The semiconductor structure includes a gate spacer formed on a sidewall surface of the gate structure, and the gate spacer is directly over the first S/D epitaxial layer. The semiconductor structure includes a dielectric spacer formed adjacent to the gate spacer, and the dielectric spacer is directly over the second epitaxial layer.
    Type: Application
    Filed: January 22, 2021
    Publication date: May 13, 2021
    Inventors: Chun-Chieh WANG, Yu-Ting LIN, Yueh-Ching PAI, Shih-Chieh CHANG, Huai-Tei YANG
  • FinFET device and method of forming
    Patent number: 11004688
    Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Min Huang, Huai-Tei Yang, Shih-Chieh Chang
  • Methods and apparatus for metrology
    Patent number: 10996568
    Abstract: Methods and apparatus for directing onto a substrate a radiation beam emitted as a result of high harmonic generation (HHG).
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 4, 2021
    Assignee: ASML Netherlands B.V
    Inventors: Petrus Wilhelmus Smorenburg, Seyed Iman Mossavat, Teis Johan Coenen
  • MEMORY DEVICE AND COMPUTING IN MEMORY METHOD THEREOF
    Publication number: 20210117187
    Abstract: A computing in memory method for a memory device is provided. The computing in memory method includes: based on a stride parameter, unfolding a kernel into a plurality of sub-kernels and a plurality of complement sub-kernels; based on the sub-kernels and the complement sub-kernels, writing a plurality of weights into a plurality of target memory cells of a memory array of the memory device; inputting an input data into a selected word line of the memory array; performing a stride operation in the memory array; temporarily storing a plurality of partial sums; and summing the stored partial sums into a stride operation result when all operation cycles are completed.
    Type: Application
    Filed: September 21, 2020
    Publication date: April 22, 2021
    Inventors: Hung-Sheng CHANG, Han-Wen HU, Yueh-Han WU, Tse-Yuan WANG, Yuan-Hao CHANG, Tei-Wei KUO
  • WINDING-TYPE COIL COMPONENT
    Publication number: 20210118608
    Abstract: A winding-type coil component includes a first wire and a second wire having a twisted wire portion where the first wire and the second wire are twisted together. Switching positions of the first wire and the second wire in the twisted wire portion are shifted in a circumferential direction of a winding core portion every turn.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kohei KOBAYASHI, Ryota HASHIMOTO, Hiroyuki TEI, Chihiro YAMAGUCHI
  • Multi BLCS for multi-state verify and multi-level QPW
    Patent number: 10984877
    Abstract: An apparatus and method for a multi-state verify of a memory array are provided. A sense circuit of a memory device is connected to a bit line of the memory array. The sense circuit includes a first voltage clamp, a second voltage clamp, and a program data latch disposed on the bit line. The first and second voltage clamps are biased to first and second voltages, respectively, where the first voltage is lower than the second voltage. When a high bias is applied to the program data latch, the program data latch is in an OFF state, and the first voltage clamp limits the bias on the bit line to the first voltage. When a low bias is applied to the program data latch, the program data latch is in an ON state, and the second voltage clamp limits the bias on the bit line to the second voltage.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: April 20, 2021
    Assignee: SanDiskTechnologies LLC
    Inventors: Jongyeon Kim, Hiroki Yabe, Kou Tei, Chia-Kai Chou, Ohwon Kwon
  • FORMATION AND IN-SITU ETCHING PROCESSES FOR METAL LAYERS
    Publication number: 20210111027
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
  • VHSA-VDDSA GENERATOR MERGING SCHEME
    Publication number: 20210104271
    Abstract: A memory device is provided including physical block circuitry including a first lateral network arrangement and a second lateral network arrangement. Each of the first and second lateral network arrangements includes a single generator configured to output both a sense amplifier voltage VHSA and a data latch voltage VDDSA, in each of a first mode and a second mode. In the first mode, during which read and program verify and other operations may occur, the generator receives VHSA as a feedback signal and in the second mode, during which programming, POR, and EVFY operations may occur, the generator receives VDDSA as a feedback signal.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 8, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Ohwon Kwon, Kou Tei, VSNK Chaitanya G.
  • VHSA-VDDSA generator merging scheme
    Patent number: 10971209
    Abstract: A memory device is provided including physical block circuitry including a first lateral network arrangement and a second lateral network arrangement. Each of the first and second lateral network arrangements includes a single generator configured to output both a sense amplifier voltage VHSA and a data latch voltage VDDSA, in each of a first mode and a second mode. In the first mode, during which read and program verify and other operations may occur, the generator receives VHSA as a feedback signal and in the second mode, during which programming, POR, and EVFY operations may occur, the generator receives VDDSA as a feedback signal.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: April 6, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Ohwon Kwon, Kou Tei, VSNK Chaitanya G
  • High-k metal gate process and device
    Patent number: 10971602
    Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Shun Liao, Huai-Tei Yang, Chun Chieh Wang, Yueh-Ching Pai, Chun-I Wu
  • MEMORY SYSTEM, METHOD OF OPERATING MEMORY, AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM
    Publication number: 20210081140
    Abstract: The present disclosure provides a memory system, a method of operating memory, and a non-transitory computer readable storage medium. The memory system includes a memory chip and a controller. The controller is coupled with the memory chip, which the controller is configured to: receive a first data corresponding to a first version from a file system in order to store the first data corresponding to the first version in a first page of the flash memory chip; and program the first data corresponding to a second version in the first page in response to the first data of the second version, which the second version is newer than the first version.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: Ping-Hsien LIN, Wei-Chen WANG, Hsiang-Pang LI, Shu-Hsien LIAO, Che-Wei TSAO, Yuan-Hao CHANG, Tei-Wei KUO
  • Pellicle and Method of Manufacturing Same
    Publication number: 20210080823
    Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Po Hsuan Li, Yu-Ting Lin, Yun-Yue Lin, Huai-Tei Yang
  • Vacuum Systems in Semiconductor Fabrication Facilities
    Publication number: 20210079522
    Abstract: Methods and devices are provided wherein rotational gas-flow is generated by vortex generators to decontaminate dirty gas (e.g., gas contaminated by solid particles) in pumping lines of vacuum systems suitable for use at a semiconductor integrated circuit fabrication facility. The vacuum systems use filterless particle decontamination units wherein rotational gas-flow is applied to separate and trap solid particles from gas prior to the gas-flow entering a vacuum pump. Methods are also described whereby solid deposits along portions of pumping lines may be dislodged and removed and portions of pumping lines may be self-cleaning.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Ming-Fa Wu, Wen-Lung Ho, Huai-Tei Yang
  • Doping for semiconductor device with conductive feature
    Patent number: 10950694
    Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Maio Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
  • Semiconductor structure with source/drain multi-layer structure and method for forming the same
    Patent number: 10937910
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
  • P-type strained channel in a fin field effect transistor (FinFET) device
    Patent number: 10930781
    Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
  • Regulator and memory device having the same
    Patent number: 10930322
    Abstract: A regulator having improved voltage control capability may include a comparator, an output voltage generator, a voltage divider, and an output voltage controller. The comparator generates a comparison voltage by comparing a reference voltage with a feedback voltage. The output voltage generator generates an output voltage by using a power supply voltage, based on the comparison voltage. The voltage divider may include a first resistor and a second resistor, which generate the feedback voltage by dividing the output voltage. The output voltage controller adjusts a resistance value of at least one of the first resistor and the second resistor, based on a result of comparing the output voltage with a target voltage.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Bon Kwang Koo, Chi Hyun Kim, Kyu Tae Park, Tei Cho
  • SEMICONDUCTOR STRUCTURE WITH SOURCE/DRAIN STRUCTURE HAVING MODIFIED SHAPE
    Publication number: 20210050433
    Abstract: Semiconductor structures and method for forming the same are provide. The semiconductor structure includes a fin structure protruding from a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes an Arsenic-doped region formed in the fin structure and a source/drain structure formed over the Arsenic-doped region. In addition, a bottommost portion of the Arsenic-doped region is lower than a bottommost portion of the source/drain structure.
    Type: Application
    Filed: November 4, 2020
    Publication date: February 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shahaji B. MORE, Shih-Chieh CHANG, Cheng-Han LEE, Huai-Tei YANG
  • Dental curable composition
    Patent number: 10918578
    Abstract: According to one aspect of the present invention, a dental curable composition includes: polymerizable monomers; inorganic particles (A1) and/or inorganic particles (A2) (excluding the inorganic particles (A2); and inorganic particles (B). The inorganic particles (A1) are surface-treated with a compound expressed by a general formula (1) and have a volume-median particle size of greater than or equal to 0.1 ?m and less than or equal to 0.9 ?m. The inorganic particles (A2) are surface-treated with a compound expressed by a general formula (2) and have a volume-median particle size of greater than or equal to 0.1 ?m and less than or equal to 0.9 ?m.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: February 16, 2021
    Assignee: GC Corporation
    Inventors: Takayuki Murata, Takumasa Kimura, Yui Tei, Azusa Miyagawa