Patents by Inventor Tei TO

Tei TO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11550709
    Abstract: A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: January 10, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wei-Chen Wang, Hung-Sheng Chang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 11545363
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
  • Publication number: 20220411800
    Abstract: The present invention is directed to provide novel RNA molecules, chimeric NA molecules, double-stranded RNA molecules, and double-stranded chimeric NA molecules. Specifically, an embodiment of the present invention is an RNA molecule for RNA interference to target a mutant allele with a point mutation, in which (1) the molecule has a nucleotide sequence complementary to a nucleotide sequence of a coding region of the mutant allele; and (2) when counted from the base at the 5?-end in a nucleotide sequence complementary to a nucleotide sequence of the mutant allele, (2-1) a base at position 5 or 6 is mismatched to a base in the mutant allele; (2-2) a position 10 or 11 corresponds to the position of the point mutation; and (2-3) a group at the 2?-position of a pentose at positions 6-8 or positions 7 and 8 is modified with, e.g., OCH3. In this RNA molecule, one or more ribonucleotides may be replaced by, e.g., a deoxyribonucleotide. The molecule may form a double-stranded RNA with a complementary strand.
    Type: Application
    Filed: July 16, 2020
    Publication date: December 29, 2022
    Applicants: The University of Tokyo, The University of Tokyo
    Inventors: Kumiko UI-TEI, Yoshiaki KOBAYASHI, Kaoru SAIGO, Yukikazu NATORI, Atsushi SATO, Yoshimasa ASANO
  • Publication number: 20220395837
    Abstract: Provided are devices, methods, and systems for temperature control of individual containers in a thermocycler for polynucleotide synthesis. Provided herein are devices, methods, and systems comprising a circuit patch having a heating element that is placed over a reaction container on a lid of the reaction container or directly over the reaction container Provided herein are devices, methods, and systems comprising a single-piece sensor assembly for a thermistor plate assembly comprising a sensor holder having a sensor pad that is in contact with the container holder.
    Type: Application
    Filed: November 16, 2020
    Publication date: December 15, 2022
    Inventors: Tei NEWMAN-LEHMAN, Eric Robert YOUNG, Thomas ROTH
  • Patent number: 11526285
    Abstract: A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: December 13, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wei-Chen Wang, Hung-Sheng Chang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 11527655
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The S/D epitaxial layer includes a first S/D epitaxial layer and a second epitaxial layer. The semiconductor structure includes a gate spacer formed on a sidewall surface of the gate structure, and the gate spacer is directly over the first S/D epitaxial layer. The semiconductor structure includes a dielectric spacer formed adjacent to the gate spacer, and the dielectric spacer is directly over the second epitaxial layer.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
  • Patent number: 11525185
    Abstract: Methods and devices are provided wherein rotational gas-flow is generated by vortex generators to decontaminate dirty gas (e.g., gas contaminated by solid particles) in pumping lines of vacuum systems suitable for use at a semiconductor integrated circuit fabrication facility. The vacuum systems use filterless particle decontamination units wherein rotational gas-flow is applied to separate and trap solid particles from gas prior to the gas-flow entering a vacuum pump. Methods are also described whereby solid deposits along portions of pumping lines may be dislodged and removed and portions of pumping lines may be self-cleaning.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Fa Wu, Wen-Lung Ho, Huai-Tei Yang
  • Patent number: 11526073
    Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po Hsuan Li, Yu-Ting Lin, Yun-Yue Lin, Huai-Tei Yang
  • Patent number: 11521675
    Abstract: A data storage system includes a storage medium coupled to a storage controller via an electrical interface connected to a plurality of input/output (IO) pads of the storage medium. The storage medium receives a read or write instruction from the storage controller via the IO pads, associates the read or write instruction with memory cells of a first block of a first plane of a plurality of planes of the storage medium, and adjusts a word line voltage level or a source line voltage level for the first block of the first plane based on (i) a position of the first plane with respect to the IO pads of the storage medium and (ii) a position of the first block within the first plane.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: December 6, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kou Tei, Anirudh Amarnath, Ohwon Kwon
  • Publication number: 20220367632
    Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 17, 2022
    Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
  • Publication number: 20220367715
    Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20220356567
    Abstract: Methods and devices are provided wherein rotational gas-flow is generated by vortex generators to decontaminate dirty gas (e.g., gas contaminated by solid particles) in pumping lines of vacuum systems suitable for use at a semiconductor integrated circuit fabrication facility. The vacuum systems use filterless particle decontamination units wherein rotational gas-flow is applied to separate and trap solid particles from gas prior to the gas-flow entering a vacuum pump. Methods are also described whereby solid deposits along portions of pumping lines may be dislodged and removed and portions of pumping lines may be self-cleaning.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Ming-Fa Wu, Wen-Lung Ho, Huai-Tei Yang
  • Publication number: 20220359003
    Abstract: A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 10, 2022
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Shu-Yin Ho, Hsiang-Pang Li, Yao-Wen Kang, Chun-Feng Wu, Yuan-Hao Chang, Tei-Wei Kuo
  • Publication number: 20220352374
    Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.
    Type: Application
    Filed: June 29, 2022
    Publication date: November 3, 2022
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
  • Publication number: 20220328450
    Abstract: Provided is a method for manufacturing a semiconductor device which connects a first bond point and a second bond point by a wire. The method includes: a ball bonding step in which a crimping ball and a ball neck are formed at the first bond point by ball bonding; a thin-walled portion forming step in which a thin-walled portion having a reduced cross-sectional area is formed between the ball neck and the crimping ball; a wire tail separating step in which after a capillary is raised to unroll a wire tail, the capillary is moved in a direction to the second bond point, and the wire tail and the crimping ball are separated in the thin-walled portion; and a wire tail joining step in which the capillary is lowered and a side surface of the separated wire tail is joined onto the crimping ball.
    Type: Application
    Filed: July 15, 2020
    Publication date: October 13, 2022
    Applicant: SHINKAWA LTD.
    Inventors: Hiroaki YOSHINO, Shinsuke TEI
  • Publication number: 20220317606
    Abstract: A fixing belt heats and fixes a toner image formed on a sheet. A plurality of heating element pieces is arranged on an opposing surface of a heater in a main scanning direction. The opposing surface faces the sheet. A heat capacity of the fixing belt and a clearance, in the main scanning direction, of a gap portion between the heating element pieces adjacent to each other have a relationship expressed as follows: (the heat capacity (J/K) of the fixing belt)?(24×(the clearance (mm))?9).
    Type: Application
    Filed: March 25, 2022
    Publication date: October 6, 2022
    Applicant: KYOCERA Document Solutions Inc.
    Inventors: Hiroki KAWASAKI, Takashi EIKI, Akihiro KONDO, Ryohei TOKUNAGA, Yuta KITABAYASHI, Rina KIKUGAWA, Shunsaku FUJII, Tei TO
  • Publication number: 20220317604
    Abstract: An image forming apparatus includes a fixing section, a detection section, and a controller. The detection section detects a passing range of a recording medium in terms of a direction intersecting with a conveyance direction of the recording medium. A heating section of the fixing section includes a first heater and a second heater. The first heater has a longitudinal direction extending in an axis direction. The second heater has a longitudinal direction extending in terms of the axis direction from each of opposite ends of the first heater in terms of the axis direction. When a result of detection by the detection section indicates that the passing range of the recording medium does not overlap with a specific range of the second heater, the controller restricts heat generation by the second heater.
    Type: Application
    Filed: March 25, 2022
    Publication date: October 6, 2022
    Applicant: KYOCERA Document Solutions Inc.
    Inventors: Shunsaku FUJII, Takashi EIKI, Akihiro KONDO, Yuta KITABAYASHI, Rina KIKUGAWA, Hiroki KAWASAKI, Tei TO, Ryohei TOKUNAGA
  • Publication number: 20220317605
    Abstract: A heater includes electrodes and heating element pieces. The electrodes energize the heating element pieces with electricity. The heating element pieces are connected to the electrodes and arranged through a gap portion in the heater in a main scanning direction. A ratio of a second surface area of the gap portion to a first surface area of the heating element pieces is 0<(second surface area of the gap portion)/(first surface area of the heating element pieces)?0.5.
    Type: Application
    Filed: March 25, 2022
    Publication date: October 6, 2022
    Applicant: KYOCERA Document Solutions Inc.
    Inventors: Rina KIKUGAWA, Takashi EIKI, Akihiro KONDO, Ryohei TOKUNAGA, Yuta KITABAYASHI, Hiroki KAWASAKI, Shunsaku FUJII, Tei TO
  • Publication number: 20220317607
    Abstract: A temperature detection section is disposed opposite to a heater so as to be out of contact with the heater, and detects a temperature of the heating element. A spacer is disposed so that the heater and the temperature detection section are out of contact with each other. The spacer includes a separator that separates the temperature detection section from the heater and that has a gap through which the heat is transferred from the heater to the temperature detection section and that melts upon the temperature of the heating element increasing to a specific temperature or higher. The separator after melting fills the gap.
    Type: Application
    Filed: March 25, 2022
    Publication date: October 6, 2022
    Applicant: KYOCERA Document Solutions Inc.
    Inventors: Tomohiro WATATANI, Yuhiro SAKAI, Takashi EIKI, Ryohei TOKUNAGA, Akihiro KONDO, Yuta KITABAYASHI, Rina KIKUGAWA, Hiroki KAWASAKI, Shunsaku FUJII, Tei TO
  • Publication number: 20220308507
    Abstract: A fixing belt heats and fixes a toner image. A pressure roller rotates the fixing belt while in contact with the fixing belt. A heater heats the fixing belt. A lubricating oil forms an oil film between the heater and an inner peripheral surface of the fixing belt. A pressure roller driver rotates the pressure roller so that the lubricating oil causes the fixing belt to be out of contact with the heater.
    Type: Application
    Filed: March 24, 2022
    Publication date: September 29, 2022
    Applicant: KYOCERA Document Solutions Inc.
    Inventors: Akihiro KONDO, Takashi EIKI, Ryohei TOKUNAGA, Yuta KITABAYASHI, Rina KIKUGAWA, Hiroki KAWASAKI, Shunsaku FUJII, Tei TO