Abstract: A semiconductor device is provided. The semiconductor device includes a metal-oxide-semiconductor field-effect-transistor (MOSFET) device electrically attachable to a first data line and a read-only memory (ROM) element. The ROM element is electrically interposable between the MOSFET device and a second data line. The ROM element includes first and second sets of memory cells in high and low resistance states, respectively, to form a secure identifier (ID).

Abstract: Provided is a read-only memory (ROM) device. The ROM device comprises a substrate that has a plurality of vertical transport field effect transistors (VFETs). The ROM device further comprises an un-activated semiconductor layer provided on each VFET. The un-activated semiconductor layer includes implanted dopants that have not been substantially activated.

Abstract: A semiconductor device formed by forming a stack of alternating horizontal nanosheet layers, recessing the stack for an n-type field effect transistor (nFET), growing crystalline semiconductor adjacent to the stack, forming vertical nanosheets from the crystalline semiconductor, forming inner spacers between the vertical nanosheets, and forming a high-k metal gate structure around the horizontal nanosheets and the vertical nanosheets.

Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor.

Abstract: Techniques regarding anchors for fins comprised within stacked VTFET devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can further comprise a fin extending from a semiconductor body. The fin can be comprised within a stacked vertical transport field effect transistor device. The apparatus can also comprise a dielectric anchor extending from the semiconductor body and adjacent to the fin. Further, the dielectric anchor can be coupled to the fin.

Abstract: A vertical field-effect transistor includes a substrate comprising a semiconductor material; a first set of fins formed from the semiconductor material and extending vertically with respect to the substrate; and a second set of fins extending vertically with respect to the substrate, wherein ones of the second set of fins abut ones of the first set of fins. The second set of fins comprises a dielectric material.

Abstract: A method comprising forming at least one fin on a substrate, wherein the at least one fin has a first section and a second section. Forming a separating layer on the substrate to isolate the second section of the fin from the first section of the fin. Forming as first set of electrical components on the first section of the at least one fin. Flipping the substrate over and removing the substrate to expose a surface of the second section of the at least one fin. Removing a portion of the second section of the at least one fin, whereby removing a portion of the second section a trench is created between sections of the separating layer and an exposed portion of the at least one fin and forming a hard mask in the trench.

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

Abstract: Provided is a read-only memory (ROM) device. The ROM device comprises a substrate that has a plurality of vertical transport field effect transistors (VFETs). The ROM device further comprises an un-activated semiconductor layer provided on each VFET. The un-activated semiconductor layer includes implanted dopants that have not been substantially activated.

Abstract: An electronic device including at least first and second superimposed transistors comprises at least a substrate; a first transistor including a portion of a first nanowire forming a first channel, and first source and drain regions in contact with ends of the first nanowire portion; and a second transistor including a portion of a second nanowire forming a second channel and having a greater length than that of the first channel, and second source and drain regions in contact with ends of the second nanowire portion such that the second transistor is arranged between the substrate and the first transistor. A dielectric encapsulation layer covers at least the second source and drain regions and such that the first source and drain regions are arranged at least partly on the dielectric encapsulation layer, and forms vertical insulating portions extending between the first and second source and drain regions.

Abstract: Ground rule verification (“GRV”) design layouts may be automatically generated based on one or more design macros. The GRV design layout may be tested based on the one or more design macros by violating one or more ground rules using one or more GRV ranges. The testing may include electrical testing of the one or more GRV design layouts based on the one or more design macros. The one or more ground rules may be automatically selected and approved the based upon a degree of violation acceptability.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of semiconductor layers on a semiconductor substrate, and forming a plurality of gate structures spaced apart from each other on the semiconductor layers. The semiconductor layers are patterned into a plurality of patterned stacks spaced apart from each other, wherein the plurality of patterned stacks are under the plurality of gate structures. The method also includes forming a plurality of sacrificial spacers on lateral sides of the plurality of gate structures, and growing a plurality of source/drain regions. The source/drain regions are adjacent the patterned stacks and include a plurality of pillar portions formed on lateral sides of the sacrificial spacers. The sacrificial spacers and the plurality of pillar portions are removed.

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

Abstract: A method comprising forming at least one fin on a substrate, wherein the at least one fin has a first section and a second section. Forming a separating layer on the substrate to isolate the second section of the fin from the first section of the fin. Forming as first set of electrical components on the first section of the at least one fin. Flipping the substrate over and removing the substrate to expose a surface of the second section of the at least one fin. Removing a portion of the second section of the at least one fin, whereby removing a portion of the second section a trench is created between sections of the separating layer and an exposed portion of the at least one fin and forming a hard mask in the trench.

Abstract: A neural network device comprises a first plurality of synapse network capacitors, wherein the synapse network capacitors of the first plurality of synapse network capacitors share a first output terminal. The neural network device further comprises a second plurality of synapse network capacitors, wherein the synapse network capacitors of the second plurality of synapse network capacitors share a second output terminal. Still further, the neural network device comprises a metal shielding disposed between the first output terminal and the second output terminal. The neural network device may be used as part of an artificial intelligence system.

Abstract: A method of fabricating a complementary metal-oxide-semiconductor device is provided. The method includes forming a work function material layer segment on a gate dielectric layer over a first vertical fin and a bottom spacer layer on an n-type bottom source/drain adjoining the first vertical fin on a first region of a substrate, wherein the gate dielectric layer is also over a second vertical fin, bottom spacer layer on a p-type bottom source/drain adjoining the second vertical fin on a second region. The method further includes heat treating the work function material layer segment to produce a modified work function material layer segment on the first vertical fin with a shifted work function value, forming a second work function material layer on the modified work function material layer segment and the gate dielectric layer on the second vertical fin, and growing a top source/drain on each of the vertical fins.

Abstract: Provided is a read-only memory (ROM) device. The ROM device comprises a substrate that has a plurality of vertical transport field effect transistors (VFETs). The ROM device further comprises an un-activated semiconductor layer provided on each VFET. The un-activated semiconductor layer includes implanted dopants that have not been substantially activated.

Abstract: Techniques facilitating forming a backside ground or power plane in stacked vertical transport field effect transistor are provided. A semiconductor structure can include a first field effect transistor (FET). The semiconductor structure can also include a second FET. The first FET can be vertically stacked on a first surface of the second FET. The second FET can be electrically coupled to a conductive plane on a second surface of the second FET, the second surface being opposite to the first surface.

Abstract: A method of fabricating a complementary metal-oxide-semiconductor device is provided. The method includes forming a work function material layer segment on a gate dielectric layer over a first vertical fin and a bottom spacer layer on an n-type bottom source/drain adjoining the first vertical fin on a first region of a substrate, wherein the gate dielectric layer is also over a second vertical fin, bottom spacer layer on a p-type bottom source/drain adjoining the second vertical fin on a second region. The method further includes heat treating the work function material layer segment to produce a modified work function material layer segment on the first vertical fin with a shifted work function value, forming a second work function material layer on the modified work function material layer segment and the gate dielectric layer on the second vertical fin, and growing a top source/drain on each of the vertical fins.