Abstract: A technique relates to a semiconductor device. A stack is formed over a bottom sacrificial layer, and the bottom sacrificial layer is on a substrate. The bottom sacrificial layer is removed so as to create an opening under the stack, and a dummy gate anchors the stack. A support structure is formed in the opening, and the support structure includes an air gap and is positioned between the stack and the substrate. One or more layers are formed on the support structure. Source or drain regions are formed over the one or more layers, such that the source or drain regions are isolated from the substrate.

Abstract: Semiconductor fins of a monolithic semiconductor structure are electrically isolated using a dielectric material at the bottoms of the fins. Relatively tall semiconductor fins can be fabricated at a relatively narrow fin pitch while avoiding mechanical instability. The semiconductor fins are grown on sidewalls of semiconductor mandrels and over a dielectric layer. The semiconductor fins are supported during mandrel removal to provide mechanical stability. The semiconductor fins can be employed as channel regions of FinFET devices.

Abstract: Fabricating a semiconductor device includes receiving a substrate structure including a substrate. The substrate structure further includes a first bottom source/drain and a first fin formed on a vertical transistor portion of the substrate and a second bottom source/drain and a second fin formed on a varactor portion of the substrate. The substrate structure further includes a bottom spacer formed on the first bottom source/drain of the vertical transistor portion and the second bottom source/drain of the varactor portion. A mask is applied to the portion of the bottom spacer formed on the first bottom source/drain. The portion of the bottom spacer formed on the second bottom source/drain of the varactor portion is removed. The mask is removed from the portion of the bottom spacer formed on the first bottom source/drain. A gate oxide is deposited on the vertical transistor portion and the varactor portion.

Abstract: A semiconductor structure includes a substrate, a vertical fin disposed over a top surface of the substrate, a first vertical transport field-effect transistor (VTFET) disposed over the top surface of the substrate surrounding a first portion of the vertical fin, an isolation layer disposed over the first VTFET surrounding a second portion of the vertical fin, and a second VTFET disposed over a top surface of the isolation layer surrounding a third portion of the vertical fin. The first portion of the vertical fin includes a first semiconductor layer with a first crystalline orientation providing a first vertical transport channel for the first VTFET, the second portion of the vertical fin includes an insulator, and the third portion of the vertical fin includes a second semiconductor layer with a second crystalline orientation providing a second vertical transport channel for the second VTFET.

Abstract: A method of making a semiconductor device includes forming a plurality of fins on a substrate, with the substrate including an oxide layer arranged beneath the plurality of fins. A sacrificial gate material is deposited on and around the plurality of fins. First trenches are formed in the sacrificial gate material. The first trenches extend through the oxide layer to a top surface of the substrate and are arranged between fins of the plurality of fin. First trenches are filled with a metal gate stack. Second trenches are formed in the sacrificial gate material, with a bottom surface of the second trenches being arranged over a bottom surface of the first trenches, and the second trenches being arranged between fins of the plurality of fins and alternating with the first trenches. The second trenches are filled with a metal gate stack.

Abstract: A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.

Abstract: A vertical transport field-effect transistor architecture is fabricated using a fin-last fabrication technique that enables pre-patterning of sacrificial gate layers and/or sacrificial source/drain layers with substantially flat topography prior to fin formation. Fins are epitaxially grown in trenches extending vertically through the device layers. Discrete regions of the sacrificial layers are later removed and replaced with appropriate source/drain and/or gate materials. Dielectric spacer elements are used to constrain feature dimensions of the replacement materials.

Abstract: Vertical field effect transistor (VFET) structures and methods of fabrication include a bottom spacer having a uniform thickness. The bottom spacer includes a bilayer portion including a first layer formed of an oxide, for example, and a second layer formed of a nitride, for example, on the first layer, and a monolayer portion of a fourth layer of a nitride for example, immediately adjacent to and intermediate the fin and the bilayer portion.

Abstract: A technique relates to fabricating a pFET device and nFET device. A contact trench is formed through an inter-level dielectric layer (ILD) and a spacer layer. The ILD is formed over the spacer layer. The contact trench exposes a p-type source/drain region of the pFET and exposes an n-type source/drain region of the NFET. A gate stack is included within the spacer layer. A p-type alloyed layer is formed on top of the p-type source/drain region in the pFET and on top of the n-type source/drain region of the nFET. The p-type alloyed layer on top of the n-type source/drain region of the nFET is converted into a metallic alloyed layer. A metallic liner layer is formed in the contact trench such that the metallic liner layer is on top of the p-type alloyed layer of the pFET and on top of the metallic alloyed layer of the nFET.

Abstract: Techniques for VFET top source and drain epitaxy are provided. In one aspect, a method of forming a VFET includes: patterning a fin to form a bottom source/drain region and a fin channel of the VFET; forming bottom spacers on the bottom source/drain region; depositing a high-? gate dielectric onto the bottom spacers and along sidewalls of the fin channel; forming gates over the bottom spacers; forming top spacers on the gates; partially recessing the fin channel to create a trench between the top spacers; forming a nitride liner along sidewalls of the trench; fully recessing the fin channel through the trench such that side portions of the fin channel remain intact; and forming a doped epitaxial top source and drain region over the fin channel. Methods not requiring a nitride liner and VFET formed using the present techniques are also provided.

Abstract: Method and structure of forming a vertical FET. The method includes depositing a bottom source-drain layer over a substrate; depositing a first heterostructure layer over the bottom source-drain layer; depositing a channel layer over the first heterostructure layer; depositing a second heterostructure layer over the channel layer; forming a first fin having a hard mask; recessing the first and the second heterostructure layers to narrow them; filling gaps with an inner spacer; laterally trimming the channel layer to a narrower width; depositing a bottom outer spacer over the bottom source-drain layer; depositing a high-k layer on the bottom outer spacer, the first fin, and the hard mask; and depositing a metal gate layer over the high-k and top outer spacer to produce the vertical FET. Forming another structure by recessing the metal gate layer below the second inner spacer.

Abstract: A method of fabricating a top source/drain junction of a vertical transistor includes forming a structure including a bottom source/drain, a fin channel extending vertically from the bottom source/drain, and a gate arranged around the fin channel, the gate including a dielectric layer, a gate metal, and spacers arranged on top and bottom surfaces of the gate; etching to form a recess in a top surface of the fin, the recess having sidewalls that form oblique angles with respect to sidewalls of the fin; forming a top source/drain on the fin and within the recess; doping the top source/drain with a dopant; and annealing to diffuse the dopants from the top source/drain into the fin.

Abstract: Nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness generally include a bilayer spacer adjacent a dummy gate disposed on a nanosheet stack. The bilayer spacer includes an inner spacer layer on sidewalls of the gate and a sacrificial layer on the inner spacer layer. The sacrificial layer can be laterally trimmed to bring the in situ doped source/drain regions closer to the channel, which improves junction sharpness. Additionally, the sacrificial spacer layer can be later removed during the process for forming the transistor so as to form an airgap spacer adjacent the gate, which minimizes parasitic capacitance.

Abstract: A method of forming a vertical transport fin field effect transistor is provided. The method includes forming a doped layer on a substrate, and forming a multilayer fin on the doped layer, where the multilayer fin includes a lower trim layer portion, an upper trim layer portion, and a fin channel portion between the upper and lower trim layer portions. A portion of the lower trim layer portion is removed to form a lower trim layer post, and a portion of the upper trim layer portion is removed to form an upper trim layer post. An upper recess filler is formed adjacent to the upper trim layer post, and a lower recess filler is formed adjacent to the lower trim layer post. A portion of the fin channel portion is removed to form a fin channel post between the upper trim layer post and lower trim layer post.

Abstract: A method of forming a vertical field effect transistor device is provided. The method includes forming one or more fin stacks on a substrate, wherein the fin stacks include a lower junction plate, a vertical fin on the top surface of the lower junction plate, and an upper junction plate on the top surface of the vertical fin. The method further includes removing a portion of the lower junction plate and upper junction plate to form recessed spaces, and forming an inner spacer in the recessed spaces. The method further includes forming a sacrificial layer on the exposed surfaces of the vertical fin and the substrate. The method further includes forming a protective liner on the sacrificial layer and inner spacers, and removing the portion of the sacrificial layer on the surface of the substrate to leave a hanging portion of the protective liner extending below the inner spacer.

Abstract: Structures and/or methods that facilitate self-aligned gate cut on a dielectric fin extension in direct stacked vertical transport field effect transistor (VTFET). A semiconductor structure can comprise a silicon on insulator (SOI) semiconductor fin comprising a dielectric fin extension. The semiconductor structure can further comprise a first vertical transport field effect transistor (VTFET) comprising a first self-aligned gate on the dielectric fin extension. The semiconductor structure can further comprise a second VTFET comprising a second self-aligned gate on the dielectric fin extension. The semiconductor structure can further comprise a gate contact extending through the dielectric fin extension through the second VTFET to the first self-aligned gate.

Abstract: A technique relates to a semiconductor device. A source or drain (S/D) contact liner is formed on one or more S/D regions. Annealing is performed to form a silicide layer around the one or more S/D regions, the silicide layer being formed at an interface between the S/D contact liner and the S/D regions. A block layer is formed into a pattern over the one or more S/D regions, such that a portion of the S/D contact liner is protected by the block layer. Unprotected portions of the S/D contact liner are removed, such that the S/D contact liner protected by the block layer remains over the one or more S/D regions. The block layer and S/D contacts are formed on the S/D contact liner over the one or more S/D regions.

Abstract: A technique relates to a semiconductor device. A source or drain (S/D) contact liner is formed on one or more S/D regions. Annealing is performed to form a silicide layer around the one or more S/D regions, the silicide layer being formed at an interface between the S/D contact liner and the S/D regions. A block layer is formed into a pattern over the one or more S/D regions, such that a portion of the S/D contact liner is protected by the block layer. Unprotected portions of the S/D contact liner are removed, such that the S/D contact liner protected by the block layer remains over the one or more S/D regions. The block layer and S/D contacts are formed on the S/D contact liner over the one or more S/D regions.

Abstract: A substrate structure includes a set of nanosheet layers stacked upon a substrate. The substrate structure includes a p-channel region and an n-channel region. The substrate structure further includes divots within the p-channel region and the n-channel region. A first liner is formed within the divots of the n-channel region. The first liner is formed of a material having a positive charge. A second liner is formed within the divots of the p-channel region. The second liner is formed of a material having a negative charge. A p-type epitaxy is deposited in the p-channel region to form first air gap spacers of the divots in the p-channel region. An n-type epitaxy is deposited in the n-channel region to form second air gap spacers of the divots in the n-channel region.

Abstract: Techniques regarding one or more VFETs operably coupled to bottom contacts with low electrical resistance are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a vertical field-effect transistor device that can comprise a semiconductor fin positioned on a source/drain region, which can comprise a semiconductor substrate. The apparatus can also comprise a metal contact layer positioned on the source/drain region and at least partially surrounding a base of the semiconductor fin. Further, the metal contact layer can be in electrical communication with the source/drain region.