Abstract: According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2×N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency.

Abstract: A magnetic memory according to an embodiment includes: a multilayer structure including a semiconductor layer and a first ferromagnetic layer; a first wiring line electrically connected to the semiconductor layer; a second wiring line electrically connected to the first ferromagnetic layer; and a voltage applying unit electrically connected between the first wiring line and the second wiring line to apply a first voltage between the semiconductor layer and the first ferromagnetic layer during a write operation, a magnetization direction of the first ferromagnetic layer being switchable by applying the first voltage.

Abstract: A cache memory has a data cache to store data per cache line, a tag to store address information of the data to be stored in the data cache, a cache controller to determine whether an address by an access request of a processor meets the address information stored in the tag and to control access to the data cache and the tag, and a write period controller to control a period required for writing data in the data cache based on at least one of an occurrence frequency of read errors to data stored in the data cache and a degree of reduction in performance of the processor due to delay in reading the data stored in the data cache.

Abstract: A resistive change memory according to an embodiment includes: a memory cell including a resistive change element comprising a first and second terminals, and a semiconductor element, the semiconductor element including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, and a third semiconductor layer of a second conductivity type that is different from the first conductivity type, the third semiconductor layer being disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer being connected to the second terminal of the resistive change element; and a read unit configured to perform a read operation by applying a first read voltage between the first terminal and the second semiconductor layer, and then applying a second read voltage that is lower than the first read voltage between the first terminal and the second semiconductor layer.

Abstract: According to an embodiment, an ID generating device includes a random number generator, a storage, and a generator. The random number generator is configured to generate random numbers. The storage is configured to store the random numbers generated by the random number generator during a predetermined time period starting from activation of the random number generator. The generator is configured to generate identification information using the random numbers stored in the storage.

Abstract: According to an embodiment, an authentication device includes an acquiring unit, a predicting unit, and an authenticating unit. The acquiring unit is configured to acquire performance information of a first device that is a device to be authenticated. The predicting unit is configured to predict performance information of a second device that is a device being a reference for authentication according to a change with time from initial performance information. The authenticating unit is configured to perform an authentication process of determining whether or not the first device falls into the second device on a basis of a degree of agreement between the performance information acquired by the acquiring unit and the performance information predicted by the predicting unit.

Abstract: A data generating device according to embodiments comprises a ring oscillator, a flip-flop circuit and a generator. The flip-flop circuit includes a first terminal and a second terminal to each of which the ring oscillator output is inputted, and that determines a value of output of the ring oscillator. The generator generates an ID for authentication based on one or more values determined by the flip-flop circuit at the time when the ring oscillator is turned on.

Abstract: A memory system according to an embodiment may have an integration unit and a prediction unit. The integration unit may detect substrate current flowing through a substrate of a non-volatile memory when the non-volatile memory with a memory cell which has binary or multivalued being the binary or more is written/erased. The integration unit may records an integration value of the detected substrate current into a storage. The prediction unit may predict a lifetime of the non-volatile memory based on the integration value which is recorded on the storage.

Abstract: A magnetic memory includes a magnetoresistive device and a load resistance unit. The magnetoresistive device has a first resistance state and a second resistance state and includes a first ferromagnetic layer and a second ferromagnetic layer. The load resistance unit is electrically connected to the magnetoresistive device. The load resistance unit is in a first state and a second state. Differential resistance of the load resistance unit at the second state is lower than differential resistance of the load resistance unit at the first state.

Abstract: According to an embodiment, an information processing system includes a time constant processor and a pattern generator. The time constant processor binarizes values indicating a plurality of unit circuits each including a gate insulating film on the basis of a time to emission indicating a time from when a defect in the gate insulating film captures a carrier in a channel current caused to flow by application of a gate voltage to the unit circuits to when the defect emits the carrier. The pattern generator generates a pattern unique to the unit circuits using the values indicating the respective unit circuits binarized by the time constant processor.

Abstract: An individual identification device (1) according to embodiments may identify a storage device (100) including one or more memory chips (40). The device comprises a first storage (40), a region allocator (15), and a hardware fingerprint generator (12). The first storage may be configured to store write data. The region allocator may be configured to write the write data in a specific region in each memory chip. The hardware fingerprint generator may be configured to generate hardware fingerprint data based on mismatch bits between the write data and read data read out from the specific region in each memory chip.

Abstract: According to an embodiment, an authentication system includes a physical device, a calculator, and an authenticator. The physical device includes a data source which outputs a data sequence along time series. The calculator performs, using hidden Markov model, probability calculation on an ID which is based on the data sequence obtained from the physical device. The authenticator authenticates the physical device based on calculation result of the calculator.

Abstract: A magnetic memory according to an embodiment includes: a multilayer structure including a semiconductor layer and a first ferromagnetic layer; a first wiring line electrically connected to the semiconductor layer; a second wiring line electrically connected to the first ferromagnetic layer; and a voltage applying unit electrically connected between the first wiring line and the second wiring line to apply a first voltage between the semiconductor layer and the first ferromagnetic layer during a write operation, a magnetization direction of the first ferromagnetic layer being switchable by applying the first voltage.

Abstract: A magnetic memory according to an embodiment includes: a multilayer structure including a semiconductor layer and a first ferromagnetic layer; a first wiring line electrically connected to the semiconductor layer; a second wiring line electrically connected to the first ferromagnetic layer; and a voltage applying unit electrically connected between the first wiring line and the second wiring line to apply a first voltage between the semiconductor layer and the first ferromagnetic layer during a write operation, a magnetization direction of the first ferromagnetic layer being switchable by applying the first voltage.

Abstract: A resistive change memory according to an embodiment includes: a memory cell including a resistive change element comprising a first and second terminals, and a semiconductor element, the semiconductor element including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, and a third semiconductor layer of a second conductivity type that is different from the first conductivity type, the third semiconductor layer being disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer being connected to the second terminal of the resistive change element; and a read unit configured to perform a read operation by applying a first read voltage between the first terminal and the second semiconductor layer, and then applying a second read voltage that is lower than the first read voltage between the first terminal and the second semiconductor layer.

Abstract: An MOSFET according to an embodiment includes: a source and drain electrodes each including a magnetic layer; a gate insulating film; and a gate electrode provided on the gate insulating film, a junction resistance on a source electrode side being greater than that on a drain electrode side, when the MOSFET is of n-channel type, the source and drain electrodes contain a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is greater than that between the Fermi surface and a conduction band minimum, and when the spin-transfer-torque switching MOSFET is of p-channel type, the source and drain electrodes containing a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is less than that between the Fermi surface and a conduction band minimum.

Abstract: According to one embodiment, a magnetic memory device includes a magnetic unit, a switching part, and a reading part. The magnetic unit includes a magnetic wire, and first and second magnetic parts. The magnetic wire includes magnetic domains and has one end and one other end. The first magnetic part is connected with the one end and has a first magnetization. The second magnetic part is connected with the one end, and has a second magnetization. The switching part includes first and second switches. The first switch is connected with the first magnetic part and flows a first current between the first magnetic part and the magnetic wire. The second switch is connected with the second magnetic part and flows a second current between the second magnetic part and the magnetic wire. The reading part is configured to read a magnetization of the magnetic domains.

Abstract: A spin transistor according to an embodiment includes: a first magnetic layer formed above a substrate and serving as one of a source and a drain; an insulating film having a lower face facing to an upper face of the first magnetic layer, an upper face opposed to the lower face, and a side face different from the lower and upper faces, the insulating film being formed on the upper face of the first magnetic layer and serving as a channel; a second magnetic layer formed on the upper face of the insulating film and serving as the other one of the source and the drain; a gate electrode formed along the side face of the insulating film; and a gate insulating film located between the gate electrode and the side face of the insulating film.

Abstract: According to one embodiment, a magnetic memory device includes a magnetic unit, a switching part, and a reading part. The magnetic unit includes a magnetic wire, and first and second magnetic parts. The magnetic wire includes magnetic domains and has one end and one other end. The first magnetic part is connected with the one end and has a first magnetization. The second magnetic part is connected with the one end, and has a second magnetization. The switching part includes first and second switches. The first switch is connected with the first magnetic part and flows a first current between the first magnetic part and the magnetic wire. The second switch is connected with the second magnetic part and flows a second current between the second magnetic part and the magnetic wire. The reading part is configured to read a magnetization of the magnetic domains.

Abstract: A stacked structure according to an embodiment includes: a semiconductor layer; a first layer formed on the semiconductor layer, the first layer containing at least one element selected from Zr, Ti, and Hf, the first layer being not thinner than a monoatomic layer and not thicker than a pentatomic layer; a tunnel barrier layer formed on the first layer; and a magnetic layer formed on the tunnel barrier layer.