Abstract: There is provided a stacked film with strong interlayer exchange coupling strength for upper and lower two magnetic layers, a magnetoresistive effect element, a semiconductor memory, and a logic LSI. A stacked film 10 includes a first magnetic layer 11, an antiferromagnetic coupling layer 12 adjacent to the first magnetic layer, and a second magnetic layer 13 adjacent to the antiferromagnetic coupling layer and antiferromagnetically coupled to the first magnetic layer. The antiferromagnetic coupling layer 12 includes a layer containing an Ir—Re alloy and has an atom proportion of Re in the Ir—Re alloy of more than 0% and 12.5% or less. The magnetoresistive effect element, the semiconductor memory, and the logic LSI include one or a plurality of the stacked films.

Abstract: A magnetic multilayer film for a magnetic memory element includes an amorphous heavy metal layer having a multilayer structure in which a plurality of first layers containing Hf alternate repeatedly with a plurality of second layers containing a heavy metal excluding Hf; and a recording layer that includes a ferromagnetic layer and that is adjacent to the heavy metal layer, the ferromagnetic layer having a variable magnetization direction.

Abstract: There is provided a stacked film that allows flowing a write current and achieves a high-density and/or high-speed memory and a magnetoresistive effect element using the stacked film. A magnetic stacked film 10 is formed of a three-layered structure that includes a first ferromagnetic layer 12, an antiferromagnetic coupling layer 10a provided on the first ferromagnetic layer 12, and a second ferromagnetic layer 16 provided on the antiferromagnetic coupling layer 10a. The antiferromagnetic coupling layer 10a includes a first non-magnetic layer 13, an interlayer coupling layer 14, and a second non-magnetic layer 15. The interlayer coupling layer 14 is selected from a metal or an alloy including at least any one of Ir, Ru, and Rh. The first non-magnetic layer 13 and the second non-magnetic layer 15 are selected from a metal or an alloy including Pt.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells each including a resistance change type memory element configured to store a resistance state and a switch, a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state so as to read information from the resistance change type memory element, and a reference signal correction unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array.

Abstract: The present invention provides an access controller, and a data transfer method. The access controller controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

Abstract: Provided are a tunnel junction stacked film having a high thermal stability, and a magnetic memory element and a magnetic memory using the tunnel junction stacked film. A tunnel junction stacked film 1 includes a recording layer 14 including a first ferromagnetic layer 24 containing boron, a tunnel junction layer 13 adjacent to the recording layer 14, and a reference layer 12 adjacent to the tunnel junction layer 13, wherein the first ferromagnetic layer 24 and the reference layer 12 are magnetized in a perpendicular direction with respect to a film surface, and the recording layer 14 includes a hafnium layer 25 adjacent to the first ferromagnetic layer 24.

Abstract: Provided are a magnetoresistive element in which the magnetization direction in a recording layer can be efficiently reversed with low resistance and without reducing reversal efficiency by a write current flowing in a heavy-metal layer; a magnetic memory; and an artificial intelligence system. A magnetoresistive element 10 includes: a heavy-metal layer 11 formed by stacking an Ir layer(s) 12 and a Pt layer(s) 13; a recording layer 16 provided to be opposed to the heavy-metal layer 11, and formed to include a first ferromagnetic layer having a reversible magnetization; a reference layer 18 formed to include a second ferromagnetic layer in which the magnetization direction is fixed; and a barrier layer 17 sandwiched between the first ferromagnetic layer and the second ferromagnetic layer, and formed of an insulator. The magnetization direction in the first ferromagnetic layer is reversed by a write current supplied to the heavy-metal layer 11.

Abstract: A computation processing device includes: a memory unit that retains computation data for weighting computation, and at least a part of which is a non-volatile storage region; a computation circuit unit that performs computation processing including the weighting computation by using a part or all of the computation data input from the memory unit; and a power gate unit that blocks power supply to a part or all of memory cells other than memory cells storing a part or all of the computation data input to the computation circuit unit in the computation processing when performing the computation processing, in the non-volatile storage region.

Abstract: A semiconductor circuit device in which a plurality of target circuits are provided and a control signal for controlling enable and disable is input to each of the plurality of target circuits, the device includes: a gating control circuit provided for each of the plurality of target circuits, in which the control signal to the corresponding target circuit is input and an On signal is output in response to the control signal for enabling the target circuit; and a power gate switch for each of the plurality of target circuits, which is provided on each power line for each of the plurality of target circuits for supplying a driving voltage to the target circuit and turned on by the On signal.

Abstract: A semiconductor circuit device includes a first clock gating circuit that outputs a first gated clock signal generated from a clock signal and a first enable signal, a non-volatile first flip-flop that operates in response to a clock pulse of the first gated clock signal, an acquisition circuit that acquires data inputted from the first flip-flop according to a second enable signal that enables or disables the acquisition of the data from the first flip-flop, and a power gating circuit that supplies electric power to the first flip-flop and receives the first and second enable signals as power source control signals. The power gating circuit includes a power switch, and supplies the electric power to the first flip-flop by turning ON the power switch when the power source control signals have logical values that enable the clock signal or the acquisition of the data in the acquisition circuit.

Abstract: A computation processing device includes: a convolutional computation unit that sequentially outputs convolutional computation result data; a pooling processing unit including a pooling computation circuit and a non-volatile storage circuit for pooling, in which the non-volatile storage circuit for pooling retains the convolutional computation result data or a computation result of the pooling computation circuit, as retained data, and the pooling computation circuit calculates and outputs pooling data subjected to pooling processing to a pooling region by using the retained data each time when the convolutional computation result data is input from the convolutional computation unit; and a power gating unit that blocks power supply to the non-volatile storage circuit for pooling while waiting for the input of the convolutional computation result data from the convolutional computation unit.

Abstract: Provided are a magnetic tunnel junction dement suppressing diffusion and penetration of constituent elements between a hard mask film, and a magnetic tunnel junction film and a protection layer, and a method for manufacturing the magnetic tunnel junction element. The magnetic tunnel junction element has a configuration in which a non-magnetic insertion layer (7) including Ta or the like is inserted beneath a hard mask layer (8).

Abstract: The present invention provides an access controller, and a data transfer method. The access controller controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

Abstract: A clustering device includes: an evaluation score calculation section configured to calculate an evaluation score or evaluation scores for evaluating a classification result; a batch process section configured to classify multiple element data into clusters with an optimum number of clusters, based on the evaluation scores respectively obtained for different number of clusters by assigning each of the multiple element data to one of the clusters; an update process section configured to assign newly added element data to a cluster that is closest to the newly added element data among the clusters into which the multiple element data are classified by the batch process section; and a determination section configured to determine validity of a classification result after assigning the newly added element data to the cluster, based on the evaluation score obtained by assigning the newly added element data to the cluster by the update process section.

Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.

Abstract: The present invention provides a device with low power and high performance, which can be applied to sensor nodes, a sensor node using the same, an access controller, a data transfer method, and execute a processing method in a microcontroller. The device has: an MRAM; a non-volatile CPU configured to include a nonvolatile memory; a non-volatile FPGA-ACC configured to include a nonvolatile memory and execute a part of operations on the nonvolatile CPU; and a power-gating control unit that controls power supply to each memory cell in the MRAM, the non-volatile CPU, and the non-volatile FPGA-ACC. The device is further provided with an access controller that controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

Abstract: The present invention relates to a platinum-based sputtering target containing platinum or a platinum alloy. The platinum-based sputtering target of the present invention is characterized by a material structure in a thickness-direction cross section thereof. Specifically, when a thickness-direction cross section is equally divided into n sections (n=5 to 20) along a thickness direction, a region including (n?2) sections excluding both end sections is set as a determination region, and when an average grain size in each of the sections is measured in the determination region, as well as an average grain size in the entire determination region is measured, the average grain size in the entire determination region is 150 ?m or less, and a coefficient of variation calculated based on the average grain size in each of the sections of the determination region is 15% or less.

Abstract: There is provided a neural network circuit device including a plurality of synapse circuits storing a synaptic coupling weight and a neuron circuit connected to the plurality of synapse circuits. The plurality of synapse circuits store the synaptic coupling weight in a non-volatile manner and output a voltage signal having a magnitude based on the stored synaptic coupling weight in response to an input signal. The neuron circuit includes a neuron MOS transistor having a floating gate and a plurality of control gates which are capacitively coupled to the floating gate and to which the voltage signals from the plurality of synapse circuits are input respectively, and a pulse generator outputting a pulse signal by turning on or off the neuron MOS transistor.

Abstract: A nonvolatile logic circuit includes: a memory unit having a pair of resistive memory elements; a computation unit connected to the memory unit and configured to perform an operation based on an input signal and a logic value corresponding to a resistance state of the pair of resistive memory elements; a determination circuit configured to determine whether the resistance state of the pair of resistive memory elements is a complementary state or a non-complementary state; and an output circuit connected to the computation unit and the determination circuit, and configured to output a signal corresponding to an operation result by the computation unit or a signal corresponding to a determination result by the determination circuit.

Abstract: Provided are a magnetoresistance effect element and a magnetic memory having a shape magnetic anisotropy and using a recording layer having an anti-parallel coupling. A first magnetic layer (3) and a second magnetic layer (5) of the magnetoresistance effect element include a ferromagnetic substance, have a magnetization direction variable to the direction perpendicular to a film surface and are magnetically coupled in an anti-parallel direction, and a junction size D (nm), which is a length of the longest straight line on an end face perpendicular to the thickness direction of the first magnetic layer (3) and the second magnetic layer (5), a film thickness t1 (nm) of the first magnetic layer (3), and a film thickness t2 (nm) of the second magnetic layer (5) satisfy relationships D<t1 and D?t1 or D?t1 and D<t2.