Abstract: Provided is a simplified driving method of a synapse circuit. In a case where a first pre-spike pulse precedes a first post-spike pulse, a second pre-spike pulse from an input circuit is used as a time window that allows writing of a coupling weight, and the first post-spike pulse from a neuron circuit is used as a write pulse for controlling a write timing of the coupling weight. In a case where the first post-spike pulse precedes the first pre-spike pulse, a second post-spike pulse from the neuron circuit is used as the time window, and the first pre-spike pulse from the input circuit is used as the write pulse. The second pre-spike pulse and the second post-spike pulse are output in synchronization with the first pre-spike pulse and the first post-spike pulse, respectively.

Abstract: A magnetoresistive effect element includes a reference layer, a barrier layer, a recording layer, and a channel layer that are disposed on top of one another, and a first terminal connected to the reference layer, and a second terminal and a third terminal connected to the channel layer. The channel layer includes a first channel layer and a second channel layer, the first channel layer has electrical resistance larger than electrical resistance of the second channel layer, the second terminal is connected to the first channel layer, and the third terminal is connected to the second channel layer, a write current flows between the second terminal and the third terminal via the first channel layer and the second channel layer, and a read current flows between the first terminal and the third terminal.

Abstract: A semiconductor circuit device in which a plurality of target circuits are provided and a control signal for controlling enable and disable is input to each of the plurality of target circuits, the device includes: a gating control circuit provided for each of the plurality of target circuits, in which the control signal to the corresponding target circuit is input and an On signal is output in response to the control signal for enabling the target circuit; and a power gate switch for each of the plurality of target circuits, which is provided on each power line for each of the plurality of target circuits for supplying a driving voltage to the target circuit and turned on by the On signal.

Abstract: Provided are a neural network device and an operating condition determination method capable of reducing power consumption. A neural network device 10 includes a processor 12, a power supply unit 14, and an operating condition determination unit 16. The processor 12 includes a logic operation circuit 21 and a memory 22, and performs, by a convolutional neural network, recognition processing on data to be processed. An output control circuit 32 of the power supply unit 14 adjusts a write current to a set value at which a recognition accuracy satisfies a preset set accuracy and that is set to be smaller than a specified value determined to switch bits in memory cells 24.

Abstract: Provided are a tunnel junction stacked film having a high thermal stability, and a magnetic memory element and a magnetic memory using the tunnel junction stacked film. A tunnel junction stacked film 1 includes a recording layer 14 including a first ferromagnetic layer 24 containing boron, a tunnel junction layer 13 adjacent to the recording layer 14, and a reference layer 12 adjacent to the tunnel junction layer 13, wherein the first ferromagnetic layer 24 and the reference layer 12 are magnetized in a perpendicular direction with respect to a film surface, and the recording layer 14 includes a hafnium layer 25 adjacent to the first ferromagnetic layer 24.

Abstract: A storage circuit includes a memory cell array of memory cells each including a variable resistance type element, a resistance-voltage conversion circuit RTj to convert a resistance value of a memory cell MCij to be read to a data voltage, a reference circuit and RTR to generate a reference voltage, a sense amplifier to determine read data by receiving the data voltage and the reference voltage via first and second input terminals, respectively, and comparing both voltages with each other, and an analog buffer circuit arranged between the resistance-voltage conversion circuit RTj and a first input terminal of the sense amplifier or between the reference circuit and RTR and a second input terminal of the sense amplifier. Current driving capability of the analog buffer circuit is large.

Abstract: A power semiconductor device includes a power semiconductor chip and a fourth electrode. The power semiconductor chip has a first surface and a second surface opposite to each other and includes a first electrode and a second electrode on the first surface thereof, and a third electrode on the second surface thereof. The first electrode is provided in a main cell area of the first surface. The fourth electrode is provided on the first surface of the power semiconductor chip, is electrically connected to the first electrode, and has an overhanging portion that extends outwardly from an outer edge of the power semiconductor chip.

Abstract: A computation processing device includes: a memory unit that retains computation data for weighting computation, and at least a part of which is a non-volatile storage region; a computation circuit unit that performs computation processing including the weighting computation by using a part or all of the computation data input from the memory unit; and a power gate unit that blocks power supply to a part or all of memory cells other than memory cells storing a part or all of the computation data input to the computation circuit unit in the computation processing when performing the computation processing, in the non-volatile storage region.

Abstract: A storage circuit includes a memory cell array of memory cells each including a variable resistance type element, a resistance-voltage conversion circuit RTj to convert a resistance value of a memory cell MCij to be read to a data voltage, a reference circuit and RTR to generate a reference voltage, a sense amplifier to determine read data by receiving the data voltage and the reference voltage via first and second input terminals, respectively, and comparing both voltages with each other, and an analog buffer circuit arranged between the resistance-voltage conversion circuit RTj and a first input terminal of the sense amplifier or between the reference circuit and RTR and a second input terminal of the sense amplifier. Current driving capability of the analog buffer circuit is large.

Abstract: A magnetoresistance effect element includes a first reference layer, a first junction layer, a first divided recording layer, a second junction layer, a second divided recording layer, and a third junction layer. The first divided recording layer has a configuration having a high magnetoresistance ratio (MR ratio), and the second divided recording layer (3) has a configuration having a high effective magnetic anisotropy energy density (Kefft).

Abstract: Provided are a magnetic film, a magnetoresistance effect element and a magnetic memory which take advantages of atop-pinned structure and a bottom-pinned structure, maintain perpendicular magnetic anisotropy of magnetic layers in a fixing layer and allow strong pinning even in an annealing treatment after a protective film is formed. A fixing layer of a magnetic film has a basic configuration in which a first magnetic layer (21), a first non-magnetic layer (31), a first Pt layer (41), a second magnetic layer (22) disposed adjacent to each other in this order. The magnetization directions of the first magnetic layer (21) and the second magnetic layer (22) are both a direction perpendicular to the film surface, and an antiferromagnetic coupling is formed between the first magnetic layer (21) and the second magnetic layer (22).

Abstract: A silicon wafer is a Czochralski wafer formed of silicon. The wafer includes a bulk layer having an oxygen concentration of 0.5×1018/cm3 or more; and a surface layer extending from the surface of the wafer to 300 nm in depth, and having an oxygen concentration of 2×1018/cm3 or more.

Abstract: The present invention relates to a platinum-based sputtering target containing platinum or a platinum alloy. The platinum-based sputtering target of the present invention is characterized by a material structure in a thickness-direction cross section thereof. Specifically, when a thickness-direction cross section is equally divided into n sections (n=5 to 20) along a thickness direction, a region including (n?2) sections excluding both end sections is set as a determination region, and when an average grain size in each of the sections is measured in the determination region, as well as an average grain size in the entire determination region is measured, the average grain size in the entire determination region is 150 ?m or less, and a coefficient of variation calculated based on the average grain size in each of the sections of the determination region is 15% or less.

Abstract: There is provided a stacked film with strong interlayer exchange coupling strength for upper and lower two magnetic layers, a magnetoresistive effect element, a semiconductor memory, and a logic LSI. A stacked film 10 includes a first magnetic layer 11, an antiferromagnetic coupling layer 12 adjacent to the first magnetic layer, and a second magnetic layer 13 adjacent to the antiferromagnetic coupling layer and antiferromagnetically coupled to the first magnetic layer. The antiferromagnetic coupling layer 12 includes a layer containing an Ir—Re alloy and has an atom proportion of Re in the Ir—Re alloy of more than 0% and 12.5% or less. The magnetoresistive effect element, the semiconductor memory, and the logic LSI include one or a plurality of the stacked films.

Abstract: A magnetic multilayer film for a magnetic memory element includes an amorphous heavy metal layer having a multilayer structure in which a plurality of first layers containing Hf alternate repeatedly with a plurality of second layers containing a heavy metal excluding Hf; and a recording layer that includes a ferromagnetic layer and that is adjacent to the heavy metal layer, the ferromagnetic layer having a variable magnetization direction.

Abstract: There is provided a stacked film that allows flowing a write current and achieves a high-density and/or high-speed memory and a magnetoresistive effect element using the stacked film. A magnetic stacked film 10 is formed of a three-layered structure that includes a first ferromagnetic layer 12, an antiferromagnetic coupling layer 10a provided on the first ferromagnetic layer 12, and a second ferromagnetic layer 16 provided on the antiferromagnetic coupling layer 10a. The antiferromagnetic coupling layer 10a includes a first non-magnetic layer 13, an interlayer coupling layer 14, and a second non-magnetic layer 15. The interlayer coupling layer 14 is selected from a metal or an alloy including at least any one of Ir, Ru, and Rh. The first non-magnetic layer 13 and the second non-magnetic layer 15 are selected from a metal or an alloy including Pt.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells each including a resistance change type memory element configured to store a resistance state and a switch, a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state so as to read information from the resistance change type memory element, and a reference signal correction unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array.

Abstract: The present invention provides an access controller, and a data transfer method. The access controller controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

Abstract: Provided are a tunnel junction stacked film having a high thermal stability, and a magnetic memory element and a magnetic memory using the tunnel junction stacked film. A tunnel junction stacked film 1 includes a recording layer 14 including a first ferromagnetic layer 24 containing boron, a tunnel junction layer 13 adjacent to the recording layer 14, and a reference layer 12 adjacent to the tunnel junction layer 13, wherein the first ferromagnetic layer 24 and the reference layer 12 are magnetized in a perpendicular direction with respect to a film surface, and the recording layer 14 includes a hafnium layer 25 adjacent to the first ferromagnetic layer 24.

Abstract: Provided are a magnetoresistive element in which the magnetization direction in a recording layer can be efficiently reversed with low resistance and without reducing reversal efficiency by a write current flowing in a heavy-metal layer; a magnetic memory; and an artificial intelligence system. A magnetoresistive element 10 includes: a heavy-metal layer 11 formed by stacking an Ir layer(s) 12 and a Pt layer(s) 13; a recording layer 16 provided to be opposed to the heavy-metal layer 11, and formed to include a first ferromagnetic layer having a reversible magnetization; a reference layer 18 formed to include a second ferromagnetic layer in which the magnetization direction is fixed; and a barrier layer 17 sandwiched between the first ferromagnetic layer and the second ferromagnetic layer, and formed of an insulator. The magnetization direction in the first ferromagnetic layer is reversed by a write current supplied to the heavy-metal layer 11.