Abstract: A computation processing device includes: a convolutional computation unit that sequentially outputs convolutional computation result data; a pooling processing unit including a pooling computation circuit and a non-volatile storage circuit for pooling, in which the non-volatile storage circuit for pooling retains the convolutional computation result data or a computation result of the pooling computation circuit, as retained data, and the pooling computation circuit calculates and outputs pooling data subjected to pooling processing to a pooling region by using the retained data each time when the convolutional computation result data is input from the convolutional computation unit; and a power gating unit that blocks power supply to the non-volatile storage circuit for pooling while waiting for the input of the convolutional computation result data from the convolutional computation unit.

Abstract: Provided are a magnetic tunnel junction dement suppressing diffusion and penetration of constituent elements between a hard mask film, and a magnetic tunnel junction film and a protection layer, and a method for manufacturing the magnetic tunnel junction element. The magnetic tunnel junction element has a configuration in which a non-magnetic insertion layer (7) including Ta or the like is inserted beneath a hard mask layer (8).

Abstract: The present invention provides an access controller, and a data transfer method. The access controller controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

Abstract: A clustering device includes: an evaluation score calculation section configured to calculate an evaluation score or evaluation scores for evaluating a classification result; a batch process section configured to classify multiple element data into clusters with an optimum number of clusters, based on the evaluation scores respectively obtained for different number of clusters by assigning each of the multiple element data to one of the clusters; an update process section configured to assign newly added element data to a cluster that is closest to the newly added element data among the clusters into which the multiple element data are classified by the batch process section; and a determination section configured to determine validity of a classification result after assigning the newly added element data to the cluster, based on the evaluation score obtained by assigning the newly added element data to the cluster by the update process section.

Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.

Abstract: The present invention provides a device with low power and high performance, which can be applied to sensor nodes, a sensor node using the same, an access controller, a data transfer method, and execute a processing method in a microcontroller. The device has: an MRAM; a non-volatile CPU configured to include a nonvolatile memory; a non-volatile FPGA-ACC configured to include a nonvolatile memory and execute a part of operations on the nonvolatile CPU; and a power-gating control unit that controls power supply to each memory cell in the MRAM, the non-volatile CPU, and the non-volatile FPGA-ACC. The device is further provided with an access controller that controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

Abstract: The present invention relates to a platinum-based sputtering target containing platinum or a platinum alloy. The platinum-based sputtering target of the present invention is characterized by a material structure in a thickness-direction cross section thereof. Specifically, when a thickness-direction cross section is equally divided into n sections (n=5 to 20) along a thickness direction, a region including (n?2) sections excluding both end sections is set as a determination region, and when an average grain size in each of the sections is measured in the determination region, as well as an average grain size in the entire determination region is measured, the average grain size in the entire determination region is 150 ?m or less, and a coefficient of variation calculated based on the average grain size in each of the sections of the determination region is 15% or less.

Abstract: There is provided a neural network circuit device including a plurality of synapse circuits storing a synaptic coupling weight and a neuron circuit connected to the plurality of synapse circuits. The plurality of synapse circuits store the synaptic coupling weight in a non-volatile manner and output a voltage signal having a magnitude based on the stored synaptic coupling weight in response to an input signal. The neuron circuit includes a neuron MOS transistor having a floating gate and a plurality of control gates which are capacitively coupled to the floating gate and to which the voltage signals from the plurality of synapse circuits are input respectively, and a pulse generator outputting a pulse signal by turning on or off the neuron MOS transistor.

Abstract: A nonvolatile logic circuit includes: a memory unit having a pair of resistive memory elements; a computation unit connected to the memory unit and configured to perform an operation based on an input signal and a logic value corresponding to a resistance state of the pair of resistive memory elements; a determination circuit configured to determine whether the resistance state of the pair of resistive memory elements is a complementary state or a non-complementary state; and an output circuit connected to the computation unit and the determination circuit, and configured to output a signal corresponding to an operation result by the computation unit or a signal corresponding to a determination result by the determination circuit.

Abstract: Provided are a magnetoresistance effect element and a magnetic memory having a shape magnetic anisotropy and using a recording layer having an anti-parallel coupling. A first magnetic layer (3) and a second magnetic layer (5) of the magnetoresistance effect element include a ferromagnetic substance, have a magnetization direction variable to the direction perpendicular to a film surface and are magnetically coupled in an anti-parallel direction, and a junction size D (nm), which is a length of the longest straight line on an end face perpendicular to the thickness direction of the first magnetic layer (3) and the second magnetic layer (5), a film thickness t1 (nm) of the first magnetic layer (3), and a film thickness t2 (nm) of the second magnetic layer (5) satisfy relationships D<t1 and D?t1 or D?t1 and D<t2.

Abstract: A magnetoresistance effect element with a small element size can be provided which achieves both an increase in a thermal stability factor ? and a reduction in a writing current IC0 and which improves a performance index ?/IC0(?A?1) obtained by dividing the thermal stability factor ? by the writing current IC0. The magnetoresistance effect element includes a first reference layer (B1), a first junction layer (11), a first magnetic layer (21), a first non-magnetic coupling layer (31), a second magnetic layer (22), and a second junction layer (12), and a film thickness of the first non-magnetic coupling layer (31) is 0.1 nm or more and 0.3 nm or less.

Abstract: A magnetoresistance effect element with a small element size can be provided which achieves both an increase in a thermal stability factor ? and a reduction in a writing current IC0 and which improves a performance index ?/IC0(?A?1) obtained by dividing the thermal stability factor ? by the writing current IC0. The magnetoresistance effect element includes a first reference layer (B1), a first junction layer (11), a first magnetic layer (21), a first non-magnetic coupling layer (31), a second magnetic layer (22), and a second junction layer (12), and a film thickness of the first non-magnetic coupling layer (31) is 0.1 nm or more and 0.3 nm or less.

Abstract: A silicon wafer is provided which is a Czochralski wafer formed of silicon, and a method for producing the silicon wafer are provided. The wafer includes a bulk layer having an oxygen concentration of 0.5×1018/cm3 or more; and a surface layer extending from the surface of the wafer to 300 nm in depth, and having an oxygen concentration of 2×1018/cm3 or more.

Abstract: A storage circuit includes: the array of a memory cell MC including a variable-resistance element; a conversion circuit that converts the resistance value of each memory cell into the signal level of an electric signal; a reference signal generation circuit that generates a reference signal common to a plurality of columns; a correction circuit that corrects one of the signal level of the reference signal and the signal level of the electric signal for each column of the array of the memory cell; and an RW circuit that determines data stored in the memory cell belonging to a corresponding column by comparing one of the reference level and the signal level of the electric signal, corrected by the correction circuit, and the other of the reference level and the signal level of the electric signal.

Abstract: Provided is an X-type 3-terminal STT-MRAM (spin orbital torque magnetization reversal component) having a high thermal stability index ? and a low writing current IC in a balanced manner. A magnetoresistance effect element has a configuration of channel layer (1)/barrier layer non adjacent magnetic layer (2b)/barrier layer adjacent magnetic layer (2a)/barrier layer (3).

Abstract: A power semiconductor device includes a power semiconductor chip and a fourth electrode. The power semiconductor chip has a first surface and a second surface opposite to each other and includes a first electrode and a second electrode on the first surface thereof, and a third electrode on the second surface thereof. The first electrode is provided in a main cell area of the first surface. The fourth electrode is provided on the first surface of the power semiconductor chip, is electrically connected to the first electrode, and has an overhanging portion that extends outwardly from an outer edge of the power semiconductor chip.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells each including a resistance change type memory element configured to store a resistance state and a switch, a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state so as to read information from the resistance change type memory element, and a reference signal correction unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array.

Abstract: A magnetoresistive effect element includes a reference layer, a barrier layer, a recording layer, and a channel layer that are disposed on top of one another, and a first terminal connected to the reference layer, and a second terminal and a third terminal connected to the channel layer. The channel layer includes a first channel layer and a second channel layer, the first channel layer has electrical resistance larger than electrical resistance of the second channel layer, the second terminal is connected to the first channel layer, and the third terminal is connected to the second channel layer, a write current flows between the second terminal and the third terminal via the first channel layer and the second channel layer, and a read current flows between the first terminal and the third terminal.

Abstract: A perpendicular magnetization type three-terminal SOT-MRAM that does not need an external magnetic field is provided. A magnetoresistance effect element where a first magnetic layer/nonmagnetic spacer layer/recording layer are disposed in order, and the first magnetic layer and the nonmagnetic spacer layer are provided to a channel layer.

Abstract: Provided are a magnetoresistive element, a magnetic memory device, and a writing and reading method for a magnetic memory device, in which an aspect ratio of a junction portion can be decreased. A magnetoresistive element 1 of the invention, includes: a heavy metal layer 2 that is an epitaxial layer; and a junction portion 3 including a recording layer 31 that is provided on the heavy metal layer 2 and includes a ferromagnetic layer of an epitaxial layer magnetized in an in-plane direction, which is an epitaxial layer, a barrier layer 32 that is provided on the recording layer 31 and includes an insulating body, and a reference layer 33 that is provided on the barrier layer 32 and has magnetization fixed in the in-plane direction, in which the recording layer 31 is subjected to magnetization reversal by applying a write current to the heavy metal layer 2.