Patents by Inventor Tetsuo Endoh

Tetsuo Endoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11183228
    Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element; a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: November 23, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Patent number: 11152468
    Abstract: Provided is a semiconductor device. A semiconductor device includes a substrate, a buffer layer provided on the substrate, a semiconductor layer provided on the buffer layer, a body region provided at a part of a surface layer of the semiconductor layer, a source region provided at a part of a surface layer of the body region, a drain region provided at a part of the surface layer of the semiconductor layer outside the body region, a gate insulating layer provided to extend from the surface layer of the body region to a predetermined depth, a gate electrode provided on the gate insulating layer, a source electrode provided on the source region, a drain electrode provided on the drain region, and an isolation region provided to extend from the surface layer of the semiconductor layer to above the predetermined depth.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 19, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Kunihiro Tsubomi, Tetsuo Endoh, Masakazu Muraguchi
  • Patent number: 11133046
    Abstract: A data write device for a resistive memory element, the resistive memory element including: a conductive electrode provided at one end of the memory element; and a reading electrode provided at the other end of the memory element being configured to vary a resistance of the memory element by applying a write current to the conductive electrode, the data write device for the resistive memory element further includes: a writing means, an output means, and a control means. The output means is provided between a power supply and the reading electrode. As output signals, a read signal from the memory element and a monitor signal to monitor a writing status of the memory element written by the writing means are output from the output means. By the monitor signal, a termination of data-writing into the resistive memory element is detected.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: September 28, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Patent number: 11081641
    Abstract: The present invention provides a magnetoresistance effect element which has a high thermal stability factor ? and in which a magnetization direction of a recording layer is a perpendicular direction with respect to a film surface, and a magnetic memory including the same. Magnetic layers of a recording layer of the magnetoresistance effect element are divided into at least two, and an Fe composition with respect to a sum total of atomic fractions of magnetic elements in each magnetic layer is changed before stacking the magnetic layers.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: August 3, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Hiroaki Honjo, Tetsuo Endoh, Shoji Ikeda, Hideo Sato, Hideo Ohno
  • Publication number: 20210233577
    Abstract: The present invention provides a magnetoresistance effect element with a high read operation speed, a magnetic memory array, a magnetic memory device, and a write method for a magnetoresistance effect element.
    Type: Application
    Filed: April 10, 2019
    Publication date: July 29, 2021
    Inventors: Yoshiaki Saito, Shoji Ikeda, Tetsuo Endoh
  • Patent number: 11062876
    Abstract: An evaluation method for an electronic device provided with an insulating film between a pair of electrode layers includes preparing a sample that has a tunnel barrier insulating film as the insulating film; irradiating the sample with electron beams from a plurality of angles to acquire a plurality of images; and performing image processing using the plurality of images to reconstruct a stereoscopic image and generate a cross-sectional image of the sample from the stereoscopic image.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: July 13, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Masaaki Niwa, Tetsuo Endoh, Shoji Ikeda, Kosuke Kimura
  • Patent number: 11054463
    Abstract: A method and a system for measuring the thermal stability factor of a magnetic tunnel junction device, a semiconductor integrated circuit, and a production management method for the semiconductor integrated circuit, capable of measuring the thermal stability factors of individual devices in a relatively short period of time and quickly performing quality control during material development and at a production site. A meter measures change in resistance value of an evaluation MTJ for a predetermined period while causing a predetermined current to flow into the evaluation MTJ maintained at a predetermined temperature. An analyzer calculates a time constant in which a low-resistance state is maintained and a time constant in which a high-resistance state is maintained from the measured change in resistance value. A thermal stability factor of the evaluation MTJ is calculated on the basis of the calculated time constants and the predetermined current flowing into the evaluation MTJ.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: July 6, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Kenchi Ito, Tetsuo Endoh, Hideo Sato, Takashi Saito, Masakazu Muraguchi, Hideo Ohno
  • Publication number: 20210193206
    Abstract: A lookup table circuit constituting a programmable logic device includes: a memory cell array including a plurality of memory cells, each having a resistive memory element; a selection circuit connected to the memory cell array and configured to output, to the memory cell array, a single cell-select signal or two or more cell-select signals for selecting a single memory cell or two or more memory cells among the plurality of memory cells, based on input of a plurality of logic signals; and a read circuit connected to the memory cell array and configured to read data from the single memory cell or the two or more memory cells selected by the single cell-select signal or the two or more cell-select signals, among the plurality of memory cells. The selection circuit is separated from a path along which the read circuit is configured to read data from the memory cell array.
    Type: Application
    Filed: September 7, 2018
    Publication date: June 24, 2021
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Tetsuo Endoh
  • Publication number: 20210158849
    Abstract: Provided are a magnetoresistive element, a magnetic memory device, and a writing and reading method for a magnetic memory device, in which an aspect ratio of a junction portion can be decreased. A magnetoresistive element 1 of the invention, includes: a heavy metal layer 2 that is an epitaxial layer; and a junction portion 3 including a recording layer 31 that is provided on the heavy metal layer 2 and includes a ferromagnetic layer of an epitaxial layer magnetized in an in-plane direction, which is an epitaxial layer, a barrier layer 32 that is provided on the recording layer 31 and includes an insulating body, and a reference layer 33 that is provided on the barrier layer 32 and has magnetization fixed in the in-plane direction, in which the recording layer 31 is subjected to magnetization reversal by applying a write current to the heavy metal layer 2.
    Type: Application
    Filed: April 11, 2019
    Publication date: May 27, 2021
    Inventors: Yoshiaki Saito, Shoji Ikeda, Hideo Sato, Tetsuo Endoh
  • Publication number: 20210135094
    Abstract: Provided are a magnetoresistance effect element and a magnetic memory having a shape magnetic anisotropy and using a recording layer having an anti-parallel coupling. A first magnetic layer (3) and a second magnetic layer (5) of the magnetoresistance effect element include a ferromagnetic substance, have a magnetization direction variable to the direction perpendicular to a film surface and are magnetically coupled in an anti-parallel direction, and a junction size D (nm), which is a length of the longest straight line on an end face perpendicular to the thickness direction of the first magnetic layer (3) and the second magnetic layer (5), a film thickness t1 (nm) of the first magnetic layer (3), and a film thickness t2 (nm) of the second magnetic layer (5) satisfy relationships D<t1 and D?t1 or D?t1 and D<t2.
    Type: Application
    Filed: February 19, 2019
    Publication date: May 6, 2021
    Inventors: Hiroaki HONJO, Tetsuo ENDOH, Shoji IKEDA, Hideo SATO, Koichi NlSHIOKA
  • Patent number: 10998491
    Abstract: A magnetoresistance effect element is provided, which can, even in a region where the element size of the magnetoresistance effect element is small, implement stable record holding at higher temperatures, and moreover which has higher thermal stability. The magnetoresistance effect element has a configuration including reference layer (B1)/first non-magnetic layer (1)/first magnetic layer (21)/first non-magnetic insertion layer (31)/second magnetic layer (22). A magnetostatic coupling is established between the first magnetic layer (21) and the second magnetic layer (22) due to magnetostatic interaction becoming dominant.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: May 4, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Kyota Watanabe, Shunsuke Fukami, Hideo Sato, Hideo Ohno, Tetsuo Endoh
  • Publication number: 20210125654
    Abstract: A magnetic memory device includes: a memory cell array including a plurality of lines arranged parallel to one another at predetermined intervals and extending in one direction, and a plurality of memory cells connected to the plurality of lines and arranged in a matrix along an extending direction of the plurality of lines and along an arrangement direction of the plurality of lines, each of the plurality of memory cells including a magnetoresistance effect element; a selection circuit connected to the plurality of lines and configured to select non-adjacent lines that are not adjacent to one another, from the plurality of lines; and a controller connected to the selection circuit and configured to cause the selection circuit to select the non-adjacent lines and allow a write current to flow through the non-adjacent lines simultaneously in writing data on the memory cell array.
    Type: Application
    Filed: June 20, 2019
    Publication date: April 29, 2021
    Inventors: Tetsuo Endoh, Yoshiaki Saito, Shoji Ikeda
  • Publication number: 20210119114
    Abstract: There is provided a magnetoresistance effect element includes: a channel layer that extends in a first direction; a recording layer which includes a film formed from a ferromagnetic material, of which a magnetization state is changed to one of two or greater magnetization states, and which is formed on the channel layer; a non-magnetic layer that is provided on a surface of the recording layer; a reference layer which is provided on a surface of the non-magnetic layer, which includes a film formed from a ferromagnetic material, and of which a magnetization direction is fixed; a terminal pair that includes a first terminal and a second terminal which are electrically connected to the channel layer with an interval in the first direction, and to which a current pulse for bringing the recording layer to any one magnetization state with a plurality of pulses is input by flowing a current to the channel layer between the first terminal and the second terminal; and a third terminal that is electrically connected to
    Type: Application
    Filed: January 30, 2019
    Publication date: April 22, 2021
    Inventors: Shunsuke Fukami, Aleksandr Kurenkov, William Andrew Borders, Hideo Ohno, Tetsuo Endoh
  • Publication number: 20210110857
    Abstract: An integrated circuit device of the invention, includes: a first resistance variable memory element provided on a semiconductor substrate; a second resistance variable memory element provided on the semiconductor substrate; and a semiconductor circuit for controlling write and read of the first resistance variable memory element and the second resistance variable memory element, which is provided on the semiconductor substrate, in which the second resistance variable memory element has a write current that is smaller than a write current of the first resistance variable memory element, and the second resistance variable memory element is disposed farther from the semiconductor substrate than the first resistance variable memory element.
    Type: Application
    Filed: March 12, 2019
    Publication date: April 15, 2021
    Inventors: Tetsuo Endoh, Shoji Ikeda, Hiroki Koike
  • Publication number: 20210098689
    Abstract: A magnetoresistance effect element is provided, which can, even in a region where the element size of the magnetoresistance effect element is small, implement stable record holding at higher temperatures, and moreover which has higher thermal stability. The magnetoresistance effect element has a configuration including reference layer (B1)/first non-magnetic layer (1)/first magnetic layer (21)/first non magnetic insertion layer (31)/second magnetic layer (22). A magnetostatic coupling is established between the first magnetic layer (21) and the second magnetic layer (22) due to magnetostatic interaction becoming dominant.
    Type: Application
    Filed: February 6, 2016
    Publication date: April 1, 2021
    Inventors: Kyota WATANABE, Shunsuke FUKAMI, Hideo SATO, Hideo OHNO, Tetsuo ENDOH
  • Publication number: 20210091304
    Abstract: [Problem] Provided are a magnetic memory element in which an improvement in properties, such as an improvement in coercive properties or a reduction in a leak current, can be attained, a method for producing the same, and a magnetic memory. [Means for Resolution] The magnetic memory element, includes: a columnar stack ST in which a reference layer FX having a fixed magnetization direction, a barrier layer TL including a non-magnetic body, and a recording layer FR having a reversible magnetization direction are stacked in this order; and an insulating film (a second insulating film 20) which contains nitrogen and is provided to cover a lateral surface of the columnar stack, in which in one or both of the recording layer and the barrier layer, a nitrogen concentration is 7×1030 atoms/m2 or more in a position of 2 nm inside from an outer circumferential end of the columnar stack.
    Type: Application
    Filed: August 18, 2020
    Publication date: March 25, 2021
    Inventors: Tetsuo Endoh, Masaaki Niwa, Hiroaki Honjo, Hideo Sato, Shoji Ikeda, Toshinari Watanabe
  • Patent number: 10957371
    Abstract: A memory device includes a memory cell array in which plural memory cells are arranged in a matrix manner, and a mode selection part. The mode selection part has at least any two of a first mode, a second mode, a third mode and selects any operation mode. The first mode is for reading and writing 1-bit data with the first memory cell or the second memory cell. The second mode is for reading and writing the 1-bit data with a cell unit including the N first memory cells and the N second memory cells connected to a bit line pair. The third mode is for reading and writing the 1-bit data with a cell unit including the M first memory cells and the M second memory cells connected to the bit line pair. M and N are 1 or more integers which are different from each other.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: March 23, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Tetsuo Endoh, Yasuhiro Ohtomo
  • Publication number: 20210074910
    Abstract: A perpendicular magnetization type three-terminal SOT-MRAM that does not need an external magnetic field is provided. A magnetoresistance effect element where a first magnetic layer/nonmagnetic spacer layer/recording layer are disposed in order, and the first magnetic layer and the nonmagnetic spacer layer are provided to a channel layer.
    Type: Application
    Filed: February 13, 2019
    Publication date: March 11, 2021
    Inventors: Yoshiaki SAITO, Shoji IKEDA, Hideo SATO, Tetsuo ENDOH
  • Publication number: 20210057641
    Abstract: Provided are a magnetic tunnel junction dement suppressing diffusion and penetration of constituent elements between a hard mask film, and a magnetic tunnel junction film and a protection layer, and a method for manufacturing the magnetic tunnel junction element. The magnetic tunnel junction element has a configuration in which a non-magnetic insertion layer (7) including Ta or the like is inserted beneath a hard mask layer (8).
    Type: Application
    Filed: March 11, 2019
    Publication date: February 25, 2021
    Inventors: Koichi NISHIOKA, Tetsuo ENDOH, Shoji IKEDA, Hiroaki HONJO, Hideo SATO, Sadahiko MIURA
  • Patent number: 10897230
    Abstract: An amplification apparatus includes a bias circuit for supplying a bias voltage, and an amplification circuit to which the bias voltage is supplied from the bias circuit. The bias circuit includes a first current source for increasing/decreasing a first current depending on the bias voltage, and a first MOSFET with first polarity through which the first current flows, to output a first voltage from a connection between the first current source and the first MOSFET; a second current source for outputting a constant current as a second current, and a second MOSFET with second polarity through which the second current flows, to output a second voltage from a connection between the second current source and the second MOSFET; and a voltage comparator for increasing/decreasing the bias voltage such that the first and second voltages become equal, based on a difference between the first and second voltages.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: January 19, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Satoru Tanoi, Tetsuo Endoh