Abstract: Provided is a method for calculating an evaluation score of clustering quality, based on the number of clusters into which a plurality of data is clustered. The calculating the evaluation score includes: calculating a degree of internal compactness that is a sum of values, each being defined by normalizing a first index value by a first value that is based on a number of data within each cluster, the first index value indicating a degree of dispersion of data within each cluster; calculating a degree of external separation defined by normalizing a sum of a second index value for each cluster by a second value that is based on the number of clusters, the second index value indicating an index of a distance between the clusters; and calculating the evaluation score according to a predetermined formula having, as variables, the degree of internal compactness and the degree of external separation.

Abstract: A lookup table circuit constituting a programmable logic device includes: a memory cell array including a plurality of memory cells, each having a resistive memory element; a selection circuit connected to the memory cell array and configured to output, to the memory cell array, a single cell-select signal or two or more cell-select signals for selecting a single memory cell or two or more memory cells among the plurality of memory cells, based on input of a plurality of logic signals; and a read circuit connected to the memory cell array and configured to read data from the single memory cell or the two or more memory cells selected by the single cell-select signal or the two or more cell-select signals, among the plurality of memory cells. The selection circuit is separated from a path along which the read circuit is configured to read data from the memory cell array.

Abstract: A semiconductor circuit device includes a first clock gating circuit that outputs a first gated clock signal generated from a clock signal and a first enable signal, a non-volatile first flip-flop that operates in response to a clock pulse of the first gated clock signal, an acquisition circuit that acquires data inputted from the first flip-flop according to a second enable signal that enables or disables the acquisition of the data from the first flip-flop, and a power gating circuit that supplies electric power to the first flip-flop and receives the first and second enable signals as power source control signals. The power gating circuit includes a power switch, and supplies the electric power to the first flip-flop by turning ON the power switch when the power source control signals have logical values that enable the clock signal or the acquisition of the data in the acquisition circuit.

Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element, a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on the cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

Abstract: A magnetic multilayer film for a magnetic memory element includes an amorphous heavy metal layer having a multilayer structure in which a plurality of first layers containing Hf alternate repeatedly with a plurality of second layers containing a heavy metal excluding Hf; and a recording layer that includes a ferromagnetic layer and that is adjacent to the heavy metal layer, the ferromagnetic layer having a variable magnetization direction.

Abstract: A magnetic tunnel junction element (10) includes a configuration in which a reference layer (14) that includes a ferromagnetic material, a barrier layer (15) that includes O, a recording layer (16) that includes a ferromagnetic material including Co or Fe, a first protective layer (17) that includes O, and a second protective layer (18) that includes at least one of Pt, Ru, Co, Fe, CoB, FeB, or CoFeB are layered.

Abstract: Provided is a simplified driving method of a synapse circuit. In a case where a first pre-spike pulse precedes a first post-spike pulse, a second pre-spike pulse from an input circuit 20a is used as a time window that allows writing of a coupling weight, and the first post-spike pulse from a neuron circuit 17 is used as a write pulse for controlling a write timing of the coupling weight. In a case where the first post-spike pulse precedes the first pre-spike pulse, a second post-spike pulse from the neuron circuit 17 is used as the time window, and the first pre-spike pulse from the input circuit 20a is used as the write pulse. The second pre-spike pulse and the second post-spike pulse are output in synchronization with the first pre-spike pulse and the first post-spike pulse, respectively.

Abstract: There is provided a magnetoresistance effect element includes: a channel layer that extends in a first direction; a recording layer which includes a film formed from a ferromagnetic material, of which a magnetization state is changed to one of two or greater magnetization states, and which is formed on the channel layer; a non-magnetic layer that is provided on a surface of the recording layer; a reference layer which is provided on a surface of the non-magnetic layer, which includes a film formed from a ferromagnetic material, and of which a magnetization direction is fixed; a terminal pair that includes a first terminal and a second terminal which are electrically connected to the channel layer with an interval in the first direction, and to which a current pulse for bringing the recording layer to any one magnetization state with a plurality of pulses is input by flowing a current to the channel layer between the first terminal and the second terminal; and a third terminal that is electrically connected to

Abstract: A storage circuit includes a memory cell array of memory cells each including a variable resistance type element, a resistance-voltage conversion circuit RTj to convert a resistance value of a memory cell MCij to be read to a data voltage, a reference circuit and RTR to generate a reference voltage, a sense amplifier to determine read data by receiving the data voltage and the reference voltage via first and second input terminals, respectively, and comparing both voltages with each other, and an analog buffer circuit arranged between the resistance-voltage conversion circuit RTj and a first input terminal of the sense amplifier or between the reference circuit and RTR and a second input terminal of the sense amplifier. Current driving capability of the analog buffer circuit is large.

Abstract: Provided are a magnetic stacked film that is capable of improving a write efficiency, and a magnetic memory element and a magnetic memory using the magnetic stacked film. A magnetic stacked film 1 is a stacked film for a magnetic memory element 100, and includes: a heavy metal layer 2 that contains ? phase W1-xTax (0.00<x?0.30); and a recording layer 10 that includes a ferromagnetic layer 18 having a reversible magnetization direction and is adjacent to the heavy metal layer 2, in which a thickness of the heavy metal layer 2 is 2 nm or more and 8 nm or less.

Abstract: A storage circuit (11) includes memory cells (MCij), each of which includes an MTJ element, and reference cells (RCi), each of which includes a series circuit of an MTJ element set to a low-resistance state and a linear resistor (FR). A RW circuit (23j) that includes a sense amplifier is provided in each column of a memory cell array (21), and compares a data voltage on a corresponding bit line (BLj) with a reference voltage. The sense amplifier includes a pair of PMOS transistors to which the data voltage and the reference voltage are applied, a CMOS sense latch that is connected to a current path of the PMOS transistors.

Abstract: A memory device includes: a cell array that includes a first region including first memory cells and a second region including second memory cells; first word lines connected to each of the first memory cells; second word lines connected to each of the second memory cells; a first bit line commonly connected to the first memory cells and the second memory cells; a row decoder that selects one of the first word lines and one of the second word lines in parallel during a data read operation; and a sense amplifier between the first region and the second region and electrically connected to the first bit line during the data read operation.

Abstract: A magnetic memory device includes: a memory cell array including a plurality of lines arranged parallel to one another at predetermined intervals and extending in one direction, and a plurality of memory cells connected to the plurality of lines and arranged in a matrix along an extending direction of the plurality of lines and along an arrangement direction of the plurality of lines, each of the plurality of memory cells including a magnetoresistance effect element; a selection circuit connected to the plurality of lines and configured to select non-adjacent lines that are not adjacent to one another, from the plurality of lines; and a controller connected to the selection circuit and configured to cause the selection circuit to select the non-adjacent lines and allow a write current to flow through the non-adjacent lines simultaneously in writing data on the memory cell array.

Abstract: Provided is a magnetoresistance effect element in which the magnetization direction of the recording layer is perpendicular to the film surface and which has a high thermal stability factor ?, and a magnetic memory. A recording layer having a configuration of first magnetic layer/first non-magnetic coupling layer/first magnetic insertion layer/second non-magnetic coupling layer/second magnetic layer is sandwiched between the first and second non-magnetic layers and stacked so that a magnetic coupling force is generated between the first magnetic layer and the second magnetic layer.

Abstract: The present invention provides an electric power conversion device and an electric power generation system which are capable of suppressing ripples in a detected voltage and detection delay.

Abstract: The present invention provides a magnetoresistance effect element with a high read operation speed, a magnetic memory array, a magnetic memory device, and a write method for a magnetoresistance effect element.

Abstract: An integrated circuit device of the invention, includes: a first resistance variable memory element provided on a semiconductor substrate; a second resistance variable memory element provided on the semiconductor substrate; and a semiconductor circuit for controlling write and read of the first resistance variable memory element and the second resistance variable memory element, which is provided on the semiconductor substrate, in which the second resistance variable memory element has a write current that is smaller than a write current of the first resistance variable memory element, and the second resistance variable memory element is disposed farther from the semiconductor substrate than the first resistance variable memory element.

Abstract: There is provided a neural network circuit device including a plurality of synapse circuits storing a synaptic coupling weight and a neuron circuit connected to the plurality of synapse circuits. The plurality of synapse circuits store the synaptic coupling weight in a non-volatile manner and output a voltage signal having a magnitude based on the stored synaptic coupling weight in response to an input signal. The neuron circuit includes a neuron MOS transistor having a floating gate and a plurality of control gates which are capacitively coupled to the floating gate and to which the voltage signals from the plurality of synapse circuits are input respectively, and a pulse generator outputting a pulse signal by turning on or off the neuron MOS transistor.

Abstract: The present invention provides an electric power conversion device and an electric power generation system which are capable of suppressing ripples in a detected voltage and detection delay.

Abstract: A storage circuit includes: the array of a memory cell MC including a variable-resistance element; a conversion circuit that converts the resistance value of each memory cell into the signal level of an electric signal; a reference signal generation circuit that generates a reference signal common to a plurality of columns; a correction circuit that corrects one of the signal level of the reference signal and the signal level of the electric signal for each column of the array of the memory cell; and an RW circuit that determines data stored in the memory cell belonging to a corresponding column by comparing one of the reference level and the signal level of the electric signal, corrected by the correction circuit, and the other of the reference level and the signal level of the electric signal.