Abstract: The present invention provides a device with low power and high performance, which can be applied to sensor nodes, a sensor node using the same, an access controller, a data transfer method, and execute a processing method in a microcontroller. The device has: an MRAM; a non-volatile CPU configured to include a nonvolatile memory; a non-volatile FPGA-ACC configured to include a nonvolatile memory and execute a part of operations on the nonvolatile CPU; and a power-gating control unit that controls power supply to each memory cell in the MRAM, the non-volatile CPU, and the non-volatile FPGA-ACC. The device is further provided with an access controller that controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

Abstract: A memory device includes: a memory cell capable of holding data; and an ECC circuit capable of generating a correction code and detecting an error based on the correction code. The memory cell is accessed by a pipeline operation. The pipeline operation includes at least four pipeline stages including a read cycle reading data from the memory cell, an ECC cycle executing generation of the correction code or error detection for the memory cell in the ECC circuit, a wait cycle during which processing for data related to the memory cell is not executed, and a write cycle writing data into the memory cell.

Abstract: Provided are a magnetic stacked film that is capable of improving a write efficiency, and a magnetic memory element and a magnetic memory using the magnetic stacked film. A magnetic stacked film 1 is a stacked film for a magnetic memory element 100, and includes: a heavy metal layer 2 that contains ? phase W1-xTax (0.00<x?0.30); and a recording layer 10 that includes a ferromagnetic layer 18 having a reversible magnetization direction and is adjacent to the heavy metal layer 2, in which a thickness of the heavy metal layer 2 is 2 nm or more and 8 nm or less.

Abstract: A memory device includes: a cell array that includes a first region including first memory cells and a second region including second memory cells; first word lines connected to each of the first memory cells; second word lines connected to each of the second memory cells; a first bit line commonly connected to the first memory cells and the second memory cells; a row decoder that selects one of the first word lines and one of the second word lines in parallel during a data read operation; and a sense amplifier between the first region and the second region and electrically connected to the first bit line during the data read operation.

Abstract: A memory device includes: a memory cell capable of holding data; and an ECC circuit capable of generating a correction code and detecting an error based on the correction code. The memory cell is accessed by a pipeline operation. The pipeline operation includes at least four pipeline stages including a read cycle reading data from the memory cell, an ECC cycle executing generation of the correction code or error detection for the memory cell in the ECC circuit, a wait cycle during which processing for data related to the memory cell is not executed, and a write cycle writing data into the memory cell.

Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.

Abstract: A nonvolatile logic circuit includes: a memory unit having a pair of resistive memory elements; a computation unit connected to the memory unit and configured to perform an operation based on an input signal and a logic value corresponding to a resistance state of the pair of resistive memory elements; a determination circuit configured to determine whether the resistance state of the pair of resistive memory elements is a complementary state or a non-complementary state; and an output circuit connected to the computation unit and the determination circuit, and configured to output a signal corresponding to an operation result by the computation unit or a signal corresponding to a determination result by the determination circuit.

Abstract: A clustering device includes: an evaluation score calculation section configured to calculate an evaluation score or evaluation scores for evaluating a classification result; a batch process section configured to classify multiple element data into clusters with an optimum number of clusters, based on the evaluation scores respectively obtained for different number of clusters by assigning each of the multiple element data to one of the clusters; an update process section configured to assign newly added element data to a cluster that is closest to the newly added element data among the clusters into which the multiple element data are classified by the batch process section; and a determination section configured to determine validity of a classification result after assigning the newly added element data to the cluster, based on the evaluation score obtained by assigning the newly added element data to the cluster by the update process section.

Abstract: An object of the invention is to provide a magnetoresistance effect element which includes a reference layer having three or more magnetic layers and which improves a thermal stability factor ? by decreasing a write error rate using an element structure that enables a wide margin to be secured between a current at which magnetization of the reference layer is reversed and a writing current Ic of a recording layer and by reducing an effect of a stray magnetic field from the reference layer. The magnetoresistance effect element includes: a first recording layer (A1); a first non-magnetic layer (11); and a first reference layer (B1), wherein the first reference layer (B1) including n-number of a plurality of magnetic layers (21, 22, . . . , 2n) and (n?1)?number of a plurality of non-magnetic insertion layers (31, 32, . . . 3(n?1)) adjacently sandwiched by each of the plurality of magnetic layers, where n?3.

Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element, a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on the cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

Abstract: Provided are a magnetic memory element in which an improvement in properties, such as an improvement in coercive properties or a reduction in a leak current, can be attained, a method for producing the same, and a magnetic memory. The magnetic memory element, includes: a columnar stack ST in which a reference layer FX having a fixed magnetization direction, a barrier layer TL including a non-magnetic body, and a recording layer FR having a reversible magnetization direction are stacked in this order; and an insulating film which contains nitrogen and is provided to cover a lateral surface of the columnar stack, in which in one or both of the recording layer and the barrier layer, a nitrogen concentration is 7×1030 atoms/m2 or more in a position of 2 nm inside from an outer circumferential end of the columnar stack.

Abstract: Provided are a magnetic film, a magnetoresistance effect element and a magnetic memory which take advantages of atop-pinned structure and a bottom-pinned structure, maintain perpendicular magnetic anisotropy of magnetic layers in a fixing layer and allow strong pinning even in an annealing treatment after a protective film is formed. A fixing layer of a magnetic film has a basic configuration in which a first magnetic layer (21), a first non-magnetic layer (31), a first Pt layer (41), a second magnetic layer (22) disposed adjacent to each other in this order. The magnetization directions of the first magnetic layer (21) and the second magnetic layer (22) are both a direction perpendicular to the film surface, and an antiferromagnetic coupling is formed between the first magnetic layer (21) and the second magnetic layer (22).

Abstract: For implementation of a magnetoresistance effect element having a quadruple interface, a magnetoresistance effect element having a small resistance area product RA, a high magnetoresistance ratio, and a high effective magnetic anisotropy energy density Kefft* is provided. A magnetoresistance effect element includes a first reference layer (B1), a first junction layer (11), a first divided recording layer (2), a second junction layer (12), a second divided recording layer (3), and a third junction layer (13). The first divided recording layer (2) has a configuration having a high magnetoresistance ratio (MR ratio), and the second divided recording layer (3) has a configuration having a high effective magnetic anisotropy energy density (Kefft).

Abstract: The magnetic memory element (100) includes: a conductive layer that includes a heavy metal layer (10) containing a 5d transition metal; a first ferromagnetic layer (20) that is adjacent to the conductive layer and contains a ferromagnetic layer having a reversible magnetization; a barrier layer (30) that is adjacent to the first ferromagnetic layer (20) and includes an insulating material; a reference layer (40) that is adjacent to the barrier layer (30) and has at least one second ferromagnetic layer (41) having a fixed magnetization direction; a cap layer (50) that is adjacent to the reference layer (40) and includes a conductive material; a first terminal (T1) that is capable of introducing a current into one end of the heavy metal layer (10) in the longitudinal direction; a second terminal (T2) that is capable of introducing a current into the other end of the heavy metal layer (10) in the longitudinal direction; and a third terminal (T3) that is capable of introducing a current into the cap layer (50).

Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element; a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

Abstract: Provided is a semiconductor device. A semiconductor device includes a substrate, a buffer layer provided on the substrate, a semiconductor layer provided on the buffer layer, a body region provided at a part of a surface layer of the semiconductor layer, a source region provided at a part of a surface layer of the body region, a drain region provided at a part of the surface layer of the semiconductor layer outside the body region, a gate insulating layer provided to extend from the surface layer of the body region to a predetermined depth, a gate electrode provided on the gate insulating layer, a source electrode provided on the source region, a drain electrode provided on the drain region, and an isolation region provided to extend from the surface layer of the semiconductor layer to above the predetermined depth.

Abstract: A data write device for a resistive memory element, the resistive memory element including: a conductive electrode provided at one end of the memory element; and a reading electrode provided at the other end of the memory element being configured to vary a resistance of the memory element by applying a write current to the conductive electrode, the data write device for the resistive memory element further includes: a writing means, an output means, and a control means. The output means is provided between a power supply and the reading electrode. As output signals, a read signal from the memory element and a monitor signal to monitor a writing status of the memory element written by the writing means are output from the output means. By the monitor signal, a termination of data-writing into the resistive memory element is detected.

Abstract: The present invention provides a magnetoresistance effect element which has a high thermal stability factor ? and in which a magnetization direction of a recording layer is a perpendicular direction with respect to a film surface, and a magnetic memory including the same. Magnetic layers of a recording layer of the magnetoresistance effect element are divided into at least two, and an Fe composition with respect to a sum total of atomic fractions of magnetic elements in each magnetic layer is changed before stacking the magnetic layers.

Abstract: The present invention provides a magnetoresistance effect element with a high read operation speed, a magnetic memory array, a magnetic memory device, and a write method for a magnetoresistance effect element.

Abstract: An evaluation method for an electronic device provided with an insulating film between a pair of electrode layers includes preparing a sample that has a tunnel barrier insulating film as the insulating film; irradiating the sample with electron beams from a plurality of angles to acquire a plurality of images; and performing image processing using the plurality of images to reconstruct a stereoscopic image and generate a cross-sectional image of the sample from the stereoscopic image.