Abstract: A spatial information visualization apparatus in an embodiment includes a storage, a vacant space processor, a spatial information generator, and an image generator. The storage stores design dimensions of a target space, and measurement information indicating coordinates of a measurement point of the target space measured by scanning the target space from a plurality of different reference points in the target space, for each of the reference points. The vacant space processor specifies a vacant space existing in the measured space stored in the storage, on the basis of the coordinates of the measurement point of the target space included in the measurement information read for each of the reference points from the storage, coordinates of the reference point, and the design dimensions of the space.

Abstract: A magnetoresistance effect element includes first and second magnetic layers having a perpendicular magnetization direction, and a first non-magnetic layer disposed adjacent to the first magnetic layer and on a side opposite to a side on which the second magnetic layer is disposed. An interfacial perpendicular magnetic anisotropy exists at an interface between the first magnetic layer and the first non-magnetic layer, and the anisotropy causes the first magnetic layer to have a magnetization direction perpendicular to the surface if the layers. The second magnetic layer has a saturation magnetization lower than that of the first magnetic layer, and an interfacial magnetic anisotropy energy density (Ki) at the interface between the first magnetic layer and the first non-magnetic layer is greater than that of an interface between the first non-magnetic layer and second magnetic layers if being disposed adjacent each other.

Abstract: A magnetoresistance effect element includes a recording layer containing a ferromagnetic body, and including a first fixed and second magnetization regions having magnetization components fixed substantially in a direction antiparallel to the in-plane direction to each other, and a free magnetization region disposed between the first and second fixed magnetization regions and having a magnetization component invertible in the in-plane direction, a domain wall disposed between the first fixed magnetization region and the free magnetization region, and being movable within the free magnetization region, and a magnetic nanowire having a width of 40 nm or less. The thickness of the recording layer is 40 nm or less and at least half but no more than twofold the width of the magnetic nanowire. The element further includes a barrier layer disposed on the recording layer, and a reference layer disposed on the barrier layer and containing a ferromagnetic body.

Abstract: A magnetoresistance effect element (100) includes a heavy metal layer (11) that includes a heavy metal and that is formed to extend in a first direction, a recording layer (12) that includes a ferromagnetic material and that is provided adjacent to the heavy metal layer (11), a barrier layer (13) that includes an insulating material and that is provided on the recording layer (12) with being adjacent to a surface of the recording layer (12) opposite to the heavy metal layer (11), and a reference layer (14) that includes a ferromagnetic material and that is provided adjacent to a surface of the barrier layer (13), the surface being opposite to the recording layer (12). The direction of the magnetization of the reference layer (14) has a component substantially fixed in the first direction, and the direction of the magnetization of the recording layer (12) has a component variable in the first direction.

Abstract: A data-write device includes a write driver that causes a current to flow through a current path including an MTJ element or the other current path including the MTJ element in accordance with writing data to be written, thereby writing the write data into the MTJ element, a write completion detector which monitors the voltage at a first connection node or a second connection node in accordance with the write data after the writing of the write data into the MTJ element starts, detects the completion of writing of the write data based on the voltage at either node, and supplies a write completion signal indicating the completion of data write, and a write controller that terminates the writing of the write data into the MTJ element in response to the write completion signal supplied from the write completion detector.

Abstract: One end of a current path of a second field-effect transistor is connected to a gate of a first field-effect transistor. One end of a magnetic tunnel junction element is connected to one end of a current path of the first field-effect transistor. A first control terminal is connected to another end of the current path of the first field-effect transistor. A second control terminal is connected to another end of the magnetic tunnel junction element. A third control terminal is connected to another end of the current path of the second field-effect transistor.

Abstract: A magnetoresistance effect element includes a bias layer comprised of an antiferromagnetic material and having a shape in which a first length in a first direction greater than a second length in a second direction perpendicular to the first direction, a recording layer comprised of a ferromagnetic material and being disposed on the bias layer, a direction of magnetization of the recording layer being reversible, a barrier layer comprised of an insulation material and being disposed on the recording layer, and a reference layer comprised of a ferromagnetic material and being disposed on the barrier layer, a direction of magnetization of the reference layer being substantially fixed.

Abstract: A data-write device includes a write driver that causes a current to flow through a current path including an MTJ element or the other current path including the MTJ element in accordance with writing data to be written, thereby writing the write data into the MTJ element, a write completion detector which monitors the voltage at a first connection node or a second connection node in accordance with the write data after the writing of the write data into the MTJ element starts, detects the completion of writing of the write data based on the voltage at either node, and supplies a write completion signal indicating the completion of data write, and a write controller that terminates the writing of the write data into the MTJ element in response to the write completion signal supplied from the write completion detector.

Abstract: A magnetoresistance effect element includes a reference layer made of a ferromagnetic material, a recording layer made of a ferromagnetic material, and a barrier layer disposed between the reference layer and the recording layer. The reference layer and the recording layer have an in-plane magnetization direction parallel to a surface of the layers. The recording layer has a shape that has short axis and long axis perpendicular to the short axis in plan view. A first value obtained by dividing a thickness of the recording layer by a length of the short axis of the recording layer is greater than 0.3 and smaller than 1.

Abstract: A memory cell (101) is connected to a word line (WL), a bit line (BL), and a power supply line (PL), and includes a flip-flop storing data based on a change in resistance value of a magnetic tunnel junction element, and, a power gating field-effect transistor including a drain that is one end of a current path connected to the power supply line, and which has another end connected to the flip-flop. The ON and OFF states of the power gating field-effect transistor are controlled based on a control signal applied to a control terminal of the power gating field-effect transistor.

Abstract: A magnetoresistance effect element (100) includes a heavy metal layer (11) that includes a heavy metal and that is formed to extend in a first direction, a recording layer (12) that includes a ferromagnetic material and that is provided adjacent to the heavy metal layer (11), a barrier layer (13) that includes an insulating material and that is provided on the recording layer (12) with being adjacent to a surface of the recording layer (12) opposite to the heavy metal layer (11), and a reference layer (14) that includes a ferromagnetic material and that is provided adjacent to a surface of the barrier layer (13), the surface being opposite to the recording layer (12). The direction of the magnetization of the reference layer (14) has a component substantially fixed in the first direction, and the direction of the magnetization of the recording layer (12) has a component variable in the first direction.

Abstract: A memory circuit (100) includes a plurality of memory cells (50), an N-type MOSFET (30a) and an N-type MOSFET (30b). The drain of the N-type MOSFET (30a) is connected to one of a pair of bit lines, and the drain of the N-type MOSFET (30b) is connected to the other of the pair of bit lines. The gate of the N-type MOSFET (30a) is connected to the drain of the N-type MOSFET (30b), and the gate of the N-type MOSFET (30b) is connected to the drain of the N-type MOSFET (30a).

Abstract: A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of the memory structure, a writing part operable to selectively write or rewrite a value of each of the nonvolatile resistive elements in the resistive network into a maximum or a minimum corresponding to a logical value to be read when data are stored into the resistive network, and a logic circuit structure operable to use, as a logical value of the memory structure, a value obtained by comparison between the resistance value of the resistive network and the resistance value of the reference resistive network.

Abstract: A memory circuit (100) includes a plurality of memory cells (50), an N-type MOSFET (30a) and an N-type MOSFET (30b). The drain of the N-type MOSFET (30a) is connected to one of a pair of bit lines, and the drain of the N-type MOSFET (30b) is connected to the other of the pair of bit lines. The gate of the N-type MOSFET (30a) is connected to the drain of the N-type MOSFET (30b), and the gate of the N-type MOSFET (30b) is connected to the drain of the N-type MOSFET (30a).

Abstract: An integrated circuit that does not involve increase in power consumption or decrease in switching probability during a write operation that occur when a latch circuit using STT-MTJ device, etc. of the prior art is operated at high speed is provided. The integrated circuit 1 includes: a memory element 1B where write occurs when a specified period ? has elapsed after a write signal is input; and a basic circuit element 1A, which is an elementary device constituting a circuit and has a data retaining function, and characterized in that an operation frequency f1 in a first operation mode in the process of memory access of the basic circuit element 1A satisfies the following relation: ?>?1/f1(0<?1?1).

Abstract: Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell 1 in the semiconductor integrated circuit is provided with: a semiconductor pillar 2 that serves as a channel; a floating gate 5 that circumferentially covers the semiconductor pillar 2 via a tunnel insulation layer 6 on the outer circumference of the semiconductor pillar 2; and a control gate 4 that circumferentially covers the semiconductor pillar via an insulating layer 8 on the outer circumference of the semiconductor pillar 2, and that circumferentially covers the floating gate 5 via an insulating layer 7 on the outer circumference of the floating gate.

Abstract: One end of a current path of a second field-effect transistor is connected to a gate of a first field-effect transistor. One end of a magnetic tunnel junction element is connected to one end of a current path of the first field-effect transistor. A first control terminal is connected to another end of the current path of the first field-effect transistor. A second control terminal is connected to another end of the magnetic tunnel junction element. A third control terminal is connected to another end of the current path of the second field-effect transistor.

Abstract: A memory cell (101) is connected to a word line (WL), a bit line (BL), and a power supply line (PL), and includes a flip-flop storing data based on a change in resistance value of a magnetic tunnel junction element, and, a power gating field-effect transistor including a drain that is one end of a current path connected to the power supply line, and which has another end connected to the flip-flop. The ON and OFF states of the power gating field-effect transistor are controlled based on a control signal applied to a control terminal of the power gating field-effect transistor.

Abstract: A spatial information visualization apparatus in an embodiment includes a storage, a vacant space processor, a spatial information generator, and an image generator. The storage stores design dimensions of a target space, and measurement information indicating coordinates of a measurement point of the target space measured by scanning the target space from a plurality of different reference points in the target space, for each of the reference points. The vacant space processor specifies a vacant space existing in the measured space stored in the storage, on the basis of the coordinates of the measurement point of the target space included in the measurement information read for each of the reference points from the storage, coordinates of the reference point, and the design dimensions of the space.

Abstract: In one embodiment, a pipe inspecting apparatus includes a selection module configured to select first and second ultrasonic optical probes from a plurality of ultrasonic optical probes attached to a pipe. The apparatus further includes a power supplying module configured to supply power to an ultrasonic transducer of the first ultrasonic optical probe to input an ultrasonic wave from the ultrasonic transducer to the pipe and to supply the ultrasonic wave via the pipe to an optical fiber sensor of the second ultrasonic optical probe. The apparatus further includes a light detection module configured to detect laser light transmitted through the optical fiber sensor of the second ultrasonic optical probe.