Abstract: In reading of a memory unit, an read failure operation due to variation in characteristic of a transistor in a dynamic load is reduced. A read circuit that reads a voltage obtained by a voltage division of a dynamic load unit and the memory unit as an output of the memory unit includes the dynamic load unit having one end connected to a side of a power supply and the other end connected to a side of the memory unit, and a feedback unit that, by a feedback of the voltage obtained by the voltage division that is divided between the dynamic load unit and the memory unit, holds the voltage obtained by the voltage division. The dynamic load unit has an array structure in which a plurality of resistive memory elements are connected in series, in parallel, or in series-parallel. The dynamic load unit has the array structure of the resistive memory elements and this structure can suppress the read failure operation due to the variation in dynamic load.

Abstract: An amplification apparatus includes a bias circuit for supplying a bias voltage, and an amplification circuit to which the bias voltage is supplied from the bias circuit. The bias circuit includes a first current source for increasing/decreasing a first current depending on the bias voltage, and a first MOSFET with first polarity through which the first current flows, to output a first voltage from a connection between the first current source and the first MOSFET; a second current source for outputting a constant current as a second current, and a second MOSFET with second polarity through which the second current flows, to output a second voltage from a connection between the second current source and the second MOSFET; and a voltage comparator for increasing/decreasing the bias voltage such that the first and second voltages become equal, based on a difference between the first and second voltages.

Abstract: A switching circuit device includes high-side and low-side switching element circuits, and high-side and low-side drive circuits. The high-side switching element circuit includes a high-side switching element connected between an output terminal and a high-voltage terminal of a high voltage source. The low-side switching element circuit includes a low-side switching element connected between the output terminal and a reference potential terminal. The high-side drive circuit turns on the high-side switching element. The low-side drive circuit turns on the low-side switching element. The high-side drive circuit includes a bootstrap capacitor connected to a drive power source. The bootstrap capacitor is charged while the low-side switching element is ON. The high-side drive circuit applies a gate voltage to the high-side switching element while the low-side switching element is OFF. The gate voltage is defined by adding a voltage of the output terminal to a voltage of the bootstrap capacitor.

Abstract: An evaluation method for an electronic device provided with an insulating film between a pair of electrode layers includes preparing a sample that has a tunnel barrier insulating film as the insulating film; irradiating the sample with electron beams from a plurality of angles to acquire a plurality of images; and performing image processing using the plurality of images to reconstruct a stereoscopic image and generate a cross-sectional image of the sample from the stereoscopic image.

Abstract: A magnetic tunnel junction element with a high MR ratio, and can prevent a recording layer from being damaged, and magnetic memory. A reference layer includes a ferromagnetic body, and has magnetization direction fixed in the vertical direction. A barrier layer includes non-magnetic body, and disposed on one surface side of the reference layer. A recording layer is disposed to sandwich barrier layer between itself and reference layer. The recording layer includes a first ferromagnetic layer including at least one of Co and Fe, and having a magnetization direction variable in vertical direction; a first non-magnetic layer including at least one of Mg, MgO, C, Li, Al, and Si, second non-magnetic layer including at least one of Ta, Hf, W, Mo, Nb, Zr, Y, Sc, Ti, V, and Cr, and second ferromagnetic layer including at least one of Co and Fe, and having a magnetization direction variable in vertical direction.

Abstract: A spintronics element including a ferromagnetic layer containing boron, and a diffusion stopper film covering a side face of the ferromagnetic layer partially or entirely, the side face in direct contact with diffusion stopper film, so as to prevent out-diffusion of the boron contained in the ferromagnetic layer. The diffusion stopper film contains boron at a concentration higher than a concentration of the boron in a portion of the ferromagnetic layer where the ferromagnetic layer contacts the diffusion stopper film.

Abstract: A magnetoresistance effect element includes a recording layer containing a ferromagnetic body, and including a first fixed and second magnetization regions having magnetization components fixed substantially in a direction antiparallel to the in-plane direction to each other, and a free magnetization region disposed between the first and second fixed magnetization regions and having a magnetization component invertible in the in-plane direction, a domain wall disposed between the first fixed magnetization region and the free magnetization region, and being movable within the free magnetization region, and a magnetic nanowire having a width of 40 nm or less. The thickness of the recording layer is 40 nm or less and at least half but no more than twofold the width of the magnetic nanowire. The element further includes a barrier layer disposed on the recording layer, and a reference layer disposed on the barrier layer and containing a ferromagnetic body.

Abstract: A circuit design support system, a circuit design support method, a circuit design support program, and a recording medium having the program recorded thereon are provided by which a design can be performed in consideration of the stochastic operation of the stochastic operation element and the influence caused by the stochastic operation of the stochastic operation element on the operation reliability of the circuit can be evaluated.

Abstract: A magnetic tunnel junction element configured by stacking, in a following stack order, a fixed layer formed of a ferromagnetic body and in which a magnetization direction is fixed, a magnetic coupling layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body and in which the magnetization direction is fixed, a barrier layer formed of a nonmagnetic body, and a recording layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, and a recording layer formed by sandwiching an insertion layer formed of a nonmagnetic body between first and second ferromagnetic layers, wherein the magnetic coupling layer is formed using a sputtering gas in which a value of a ratio in which a mass number of an element used in the magnetic coupling layer divided by the mass number of the sputtering gas itself is 2.2 or smaller.

Abstract: A method and a system for measuring the thermal stability factor of a magnetic tunnel junction device, a semiconductor integrated circuit, and a production management method for the semiconductor integrated circuit, capable of measuring the thermal stability factors of individual devices in a relatively short period of time and quickly performing quality control during material development and at a production site. A meter measures change in resistance value of an evaluation MTJ for a predetermined period while causing a predetermined current to flow into the evaluation MTJ maintained at a predetermined temperature. An analyzer calculates a time constant in which a low-resistance state is maintained and a time constant in which a high-resistance state is maintained from the measured change in resistance value. A thermal stability factor of the evaluation MTJ is calculated on the basis of the calculated time constants and the predetermined current flowing into the evaluation MTJ.

Abstract: A memory device and a memory system capable of flexibly corresponding to the number of dimensions of reference data and having a compact circuit configuration at searching for data similar to search data are provided. A memory system capable of reducing processing time to search for data similar to search data and reducing a circuit area is provided. A memory device includes a plurality of read circuits, an input search data storing circuit configured to divide search data to output, a plurality of similarity evaluation cells and a plurality of current accumulators. The memory system is configured by including a main core and a branch core thus configured.

Abstract: A method for producing a magnetic memory includes: forming a magnetic film having a non-magnetic layer between a first magnetic layer and a second magnetic layer on a substrate having an electrode layer; performing annealing treatment at a first treatment temperature in a state where a magnetic field is applied in a direction perpendicular to a film surface of the first or the second magnetic layer in vacuum; forming a magnetic tunnel junction element; forming a protective film protecting the magnetic tunnel junction element; a formation accompanied by thermal history, in which a constituent element of a magnetic memory is formed after the protective film formation on the substrate; and implementing annealing treatment at a second treatment temperature lower than the first treatment temperature on the substrate in an annealing treatment chamber, in vacuum or inert gas wherein no magnetic field is applied.

Abstract: A magnetic tunnel junction element includes, in a following stack order, an underlayer formed of a metal material, a fixed layer formed of a ferromagnetic body, a magnetic coupling layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, and a recording layer formed of a ferromagnetic body, or alternatively, the magnetic tunnel junction element includes, in a following stack order, a recording layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body, a magnetic coupling layer formed of a nonmagnetic body, an underlayer formed of a metal material, and a fixed layer formed of a ferromagnetic body, wherein the fixed layer is formed and stacked after performing plasma treatment to a surface of the underlayer having been formed.

Abstract: Provided is a semiconductor device. A semiconductor device includes a substrate, a buffer layer provided on the substrate, a semiconductor layer provided on the buffer layer, a body region provided at a part of a surface layer of the semiconductor layer, a source region provided at a part of a surface layer of the body region, a drain region provided at a part of the surface layer of the semiconductor layer outside the body region, a gate insulating layer provided to extend from the surface layer of the body region to a predetermined depth, a gate electrode provided on the gate insulating layer, a source electrode provided on the source region, a drain electrode provided on the drain region, and an isolation region provided to extend from the surface layer of the semiconductor layer to above the predetermined depth.

Abstract: A magnetoresistance effect element includes a reference layer made of a ferromagnetic material, a recording layer made of a ferromagnetic material, and a barrier layer disposed between the reference layer and the recording layer. The reference layer and the recording layer have an in-plane magnetization direction parallel to a surface of the layers. The recording layer has a shape that has short axis and long axis perpendicular to the short axis in plan view. A first value obtained by dividing a thickness of the recording layer by a length of the short axis of the recording layer is greater than 0.3 and smaller than 1.

Abstract: A magnetoresistance effect element includes first and second magnetic layers having a perpendicular magnetization direction, and a first non-magnetic layer disposed adjacent to the first magnetic layer and on a side opposite to a side on which the second magnetic layer is disposed. An interfacial perpendicular magnetic anisotropy exists at an interface between the first magnetic layer and the first non-magnetic layer, and the anisotropy causes the first magnetic layer to have a magnetization direction perpendicular to the surface of the layers. An atomic fraction of all magnetic elements to all magnetic and non-magnetic elements included in the second magnetic layer is smaller than that of the first magnetic layer.

Abstract: A magnetic tunnel junction element (10) includes a configuration in which a reference layer (14) that includes a ferromagnetic material, a barrier layer (15) that includes O, a recording layer (16) that includes a ferromagnetic material including Co or Fe, a first protective layer (17) that includes O, and a second protective layer (18) that includes at least one of Pt, Ru, Co, Fe, CoB, FeB, or CoFeB are layered.

Abstract: A magnetoresistance effect element includes first and second magnetic layers having a perpendicular magnetization direction, and a first non-magnetic layer disposed adjacent to the first magnetic layer and on a side opposite to a side on which the second magnetic layer is disposed. An interfacial perpendicular magnetic anisotropy exists at an interface between the first magnetic layer and the first non-magnetic layer, and the anisotropy causes the first magnetic layer to have a magnetization direction perpendicular to the surface if the layers. The second magnetic layer has a saturation magnetization lower than that of the first magnetic layer, and an interfacial magnetic anisotropy energy density (Ki) at the interface between the first magnetic layer and the first non-magnetic layer is greater than that of an interface between the first non-magnetic layer and second magnetic layers if being disposed adjacent each other.

Abstract: A memory circuit (11) includes: a memory cell (MCij) including a variable-resistance element in which a resistance value varies substantially between two levels; a resistance-voltage conversion circuit that converts the resistance value of a memory cell (MCij) to be read into a data voltage; a reference circuit (RC1) including a series circuit of a variable-resistance element and a linear resistor, the variable-resistance element including substantially the same configuration as the configuration of the variable-resistance element included in the memory cell MCij and being set to a lower resistance of two levels; a reference voltage conversion circuit that converts the resistance value of the reference circuit (RCi) into a reference voltage; and a sense amplifier (SA) that determines data stored in the memory cell (MCij) by comparing the data voltage with the reference voltage.

Abstract: A spintronics element including a ferromagnetic layer containing boron, and a diffusion stopper film covering a side face of the ferromagnetic layer partially or entirely, the side face in direct contact with diffusion stopper film, so as to prevent out-diffusion of the boron contained in the ferromagnetic layer. The diffusion stopper film contains boron at a concentration higher than a concentration of the boron in a portion of the ferromagnetic layer where the ferromagnetic layer contacts the diffusion stopper film.