Patents by Inventor Tetsuya Hayashi

Tetsuya Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7852608
    Abstract: An electrostatic discharge protection circuit and a semiconductor device that prevent the breakdown of a semiconductor device caused by an electrostatic discharge (ESD) which suddenly changes. When voltage which is far higher than VDD1 is applied to a power supply line as a result of an ESD, a great electric potential difference is produced between VDD1 and VSS. At this time an electric current path for making an electric charge generated by overvoltage flow to a grounding line is formed by a clamp circuit. As a result, an electric current flows into GND of a circuit block. This prevents the production of a great electric potential difference between VDD1 and VSS. In addition, at this time a rapid change in the level of the overvoltage applied to a signal line is suppressed by a protection circuit. This prevents the dielectric breakdown of gate oxide films of transistors included in a circuit block which receives a control signal.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: December 14, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masanori Yoshitani, Tetsuya Hayashi, Tomokazu Higuchi
  • Patent number: 7842332
    Abstract: A method for intermittently applying thin-film coatings is realized, by which a coating of extremely thin film reduced to 20 ?m or less in thickness is deposited intermittently with high productivity and at the same time, the trailing coating edge of the thin film is formed in a highly accurate shape having good linearity. This is achieved as follows. A band-shaped substrate (1) traveling in one direction is kept looped over a stationary reference-roller (4) and a movable actuation roller (7), and is brought into contact with an application roller (19) which carries a coating agent (18) on its circumferential surface and rotates in a direction opposite to the direction of travel of the substrate (1). The actuation roller (7) is moved to come into or out of contact with the substrate (1) with a predetermined timing.
    Type: Grant
    Filed: November 25, 2005
    Date of Patent: November 30, 2010
    Assignee: Panasonic Corporation
    Inventors: Kazutaka Teramoto, Tetsuya Hayashi
  • Patent number: 7816038
    Abstract: A method for producing a lithium ion secondary battery includes the steps of: forming a positive electrode mixture layer on a positive electrode substrate to obtain a positive electrode; forming a negative electrode mixture layer on a negative electrode substrate to obtain a negative electrode; forming an electronically insulating porous film that is bonded to a surface of at least one of the positive electrode and the negative electrode; interposing a separator between the positive electrode and the negative electrode to form an electrode plate assembly; and impregnating the electrode plate assembly with a non-aqueous electrolyte. The step of forming a porous film includes the steps of: preparing a porous film paste that contains a film binder comprising a thermo-cross-linkable resin and a particulate filler; and applying the porous film paste onto a surface of at least one of the positive electrode and the negative electrode and heating the resultant applied film.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: October 19, 2010
    Assignee: Panasonic Corporation
    Inventors: Tsumoru Ohata, Junji Nakajima, Tetsuya Hayashi, Shigeo Ikuta, Akiko Fujino, Eitaro Nakamura
  • Patent number: 7807534
    Abstract: A method for producing a semiconductor device includes forming a first hetero-semiconductor layer as a hetero-junction to a surface of a silicon carbide epitaxial layer. This layer is composed of polycrystalline silicon having a band gap different from that of the silicon carbide epitaxial layer. An etching stopper layer composed of a material having a different etching rate from that of the polycrystalline silicon is formed on the surface of the first hetero-semiconductor layer. A second hetero-semiconductor layer composed of polycrystalline silicon is formed so that the second hetero-semiconductor layer contacts the surface of the first hetero-semiconductor layer and the etching stopper layer. The etching stopper layer is removed, the first hetero-semiconductor layer is thermally oxidized, and the thermally oxidized portion is then removed.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: October 5, 2010
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Hideaki Tanaka, Masakatsu Hoshi, Tetsuya Hayashi, Shigeharu Yamagami
  • Publication number: 20100237906
    Abstract: A receiving circuit includes an impedance compensating circuit, a first input terminal and a second input terminal coupled to a first signal line and a second signal line, a first signal and a second signal corresponding to differential signals being transmitted at the first input terminal and the second input terminal, respectively, a signal input circuit, coupled to the first input terminal and the second input terminal, which receives the first signal and the second signal are input, and a differential-signal detector that detects whether or not the differential signals are supplied to the first input terminal and the second input terminal.
    Type: Application
    Filed: January 29, 2010
    Publication date: September 23, 2010
    Applicant: FUJITSU MIRCOELECTRONICS LIMITED
    Inventors: Tetsuya HAYASHI, Daisuke Suzuki
  • Patent number: 7790218
    Abstract: A method for forming an electrode for a battery includes the step of rotating a gravure roll while allowing the gravure roll to abut against the surface of an electrode, thereby applying a coating fluid serving as a precursor of a porous layer on the surface of the electrode. In this step, part of the coating fluid applied to the surface of the electrode is continuously removed by allowing a scraper to abut against the surface of the electrode, and the width of a part of the scraper abutting against the surface of the electrode is adjusted according to variations in the width of each of linear portions of the porous layer left after the removal of the part of the coating fluid.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: September 7, 2010
    Assignee: Panasonic Corporation
    Inventor: Tetsuya Hayashi
  • Patent number: 7781802
    Abstract: As semiconductor regions in contact with a first main surface of a semiconductor base composed by forming an N? silicon carbide epitaxial layer on an N+ silicon carbide substrate connected to a cathode electrode, there are provided both of an N+ polycrystalline silicon layer of a same conduction type as a conduction type of the semiconductor base and a P+ polycrystalline silicon layer of a conduction type different from the conduction type of the semiconductor base. Both of the N+ polycrystalline silicon layer and the P+ polycrystalline silicon layer are hetero-joined to the semiconductor base, and are ohmically connected to the anode electrode.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: August 24, 2010
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Shigeharu Yamagami, Masakatsu Hoshi, Yoshio Shimoida, Tetsuya Hayashi, Hideaki Tanaka
  • Patent number: 7781786
    Abstract: Impurity concentration of a second semiconductor region is set such that when a predetermined reverse bias is applied to a heterojunction diode configured by a first semiconductor region and the second semiconductor region, a breakdown voltage at least in a heterojunction region other than outer peripheral ends of the heterojunction diode is a breakdown voltage of a semiconductor device.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: August 24, 2010
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Yoshio Shimoida, Hideaki Tanaka, Shigeharu Yamagami
  • Patent number: 7768035
    Abstract: A semiconductor device has a semiconductor base of a first conductivity type; a hetero semiconductor region in contact with the semiconductor base; a gate electrode adjacent to a portion of a junction between the hetero semiconductor region and the semiconductor base across a gate insulating film; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor base. The hetero semiconductor region has a band gap different from that of the semiconductor base. The hetero semiconductor region includes a first hetero semiconductor region and a second hetero semiconductor region. The first hetero semiconductor region is formed before the gate insulating film is formed. The second hetero semiconductor region is formed after the gate insulating film is formed.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: August 3, 2010
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Yoshio Shimoida, Tetsuya Hayashi, Masakatsu Hoshi, Hideaki Tanaka, Shigeharu Yamagami
  • Publication number: 20100190063
    Abstract: At least (i) dispersing and mixing inorganic oxide filler, solvent and binder so as to produce a coating paint; (ii) supplying the coating paint to a gravure coater; and (iii) coating the coating paint to member via a gravure roll are included. The (i) or (ii) includes allowing the coating paint to stand still and removing an aggregate and a precipitate of inorganic oxide filler.
    Type: Application
    Filed: June 18, 2007
    Publication date: July 29, 2010
    Inventors: Yusuke Fukumoto, Tetsuya Hayashi, Kazunori Kubota
  • Patent number: 7758998
    Abstract: A lithium ion secondary battery includes a positive electrode capable of absorbing and desorbing lithium ion, a negative electrode capable of absorbing and desorbing lithium ion, a porous film interposed between the positive electrode and the negative electrode, and a non-aqueous electrolyte: the porous film being adhered to a surface of at least one of the positive electrode and the negative electrode; the porous film including a filler and a resin binder; the resin binder content in the porous film being 1.5 to 8 parts by weight per 100 parts by weight of the filler; and the resin binder including an acrylonitrile unit, an acrylate unit, or a methacrylate unit.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: July 20, 2010
    Assignee: Panasonic Corporation
    Inventors: Tsumoru Ohata, Junji Nakajima, Tetsuya Hayashi, Takashi Takano, Shigeo Ikuta, Kohei Suzuki, Kouji Nishida, Masao Fukunaga, Akiko Fujino
  • Patent number: 7754377
    Abstract: A lithium ion secondary battery includes a positive electrode capable of absorbing and desorbing lithium ion, a negative electrode capable of absorbing and desorbing lithium ion, a porous film interposed between the positive electrode and the negative electrode, and a non-aqueous electrolyte: the porous film being adhered to a surface of at least one of the positive electrode and the negative electrode; the porous film including a filler and a resin binder; the resin binder content in the porous film being 1.5 to 8 parts by weight per 100 parts by weight of the filler; and the resin binder including an acrylonitrile unit, an acrylate unit, or a methacrylate unit.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: July 13, 2010
    Assignee: Panasonic Corporation
    Inventors: Tsumoru Ohata, Junji Nakajima, Tetsuya Hayashi, Takashi Takano, Shigeo Ikuta, Kohei Suzuki, Kouji Nishida, Masao Fukunaga, Akiko Fujino
  • Patent number: 7749845
    Abstract: A method of manufacturing a semiconductor device having a polycrystalline silicon layer (5) includes; a step of forming a mask layer (7) on the polycrystalline silicon layer (5); a step of forming a side wall (8) that is provided on a side face of the mask layer (7) and covers part of the polycrystalline silicon layer (6); a step of doping an impurity (52) into the polycrystalline silicon layer (5) by using at least one of the mask layer (7) and the side wall (8) as a mask; and a step of etching the polycrystalline silicon layer (5, 6) by using at least one of the mask layer (7) and the side wall (8) as a mask.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: July 6, 2010
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Shigeharu Yamagami, Masakatsu Hoshi, Tetsuya Hayashi, Hideaki Tanaka, Yoshio Shimoida
  • Publication number: 20100165808
    Abstract: There are provided at least a first information storage area 20A and a second information storage area 40A. The first information storage area 20A contains, in advance, an OS or mpeg data. The second information storage area 40A is either write-once or rewriteable and available for writing OS update information or movie correction information. The configuration enables easy backup and restoration of software, content, and various information including update information for use by the software and content with reduced user time and workload.
    Type: Application
    Filed: December 22, 2009
    Publication date: July 1, 2010
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yasuhiro Harada, Shigemi Maeda, Hideharu Tajima, Tetsuya Hayashi, Atsushi Etoh
  • Patent number: 7745042
    Abstract: A lithium ion secondary battery in which an abnormal overheat due to a short circuit of a current collecting portion of one electrode and an electrode material mixture of the other is prevented. The lithium ion secondary battery has: a positive electrode including a core material having a current collecting portion and a material mixture carrying portion and a material mixture layer carried thereon; a negative electrode including a core material having a current collecting portion and a material mixture carrying portion and a material mixture layer carried thereon; a separator and a porous electron-insulating layer including an inorganic oxide filler and a binder both interposed between the positive and negative electrodes; and a non-aqueous electrolyte. The insulating layer is carried on a region including surfaces of the positive electrode current collecting portion and material mixture layer, and/or a region including surfaces of the negative electrode current collecting portion and material mixture layer.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: June 29, 2010
    Assignee: Panasonic Corporation
    Inventors: Akiko Fujino, Tsumoru Ohata, Tetsuya Hayashi
  • Patent number: 7743901
    Abstract: A parking lock releasing apparatus includes a manipulator element operable to select a parking range of an automatic transmission, a sensor operable to detect a selection by the manipulator element, an actuator operable to operate a parking lock mechanism of the automatic transmission based on a detection by the sensor, and a manual lever operable to manually release an operation of the parking lock mechanism. The manual lever is operable on condition that a parking brake device is in operation.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: June 29, 2010
    Assignee: Honda Motor Co., Ltd.
    Inventors: Tetsuya Hayashi, Naoki Osawa
  • Publication number: 20100154704
    Abstract: A method for producing lithium ion secondary batteries includes the steps of: (A) preparing an electrode sheet with lead-forming parts, (B) intermittently forming porous insulating layers containing an inorganic oxide filler and a binder on a surface of the electrode sheet excluding the lead-forming parts, (C) connecting a lead to each of the lead-forming parts, and (D) fabricating batteries by using the electrode sheet to which the leads are connected. The step B includes: the step of applying a slurry containing the inorganic oxide filler and the binder to the outer surface of a gravure roll, and transferring the slurry applied to the outer surface of the gravure roll on a surface of the electrode sheet that is being transported by a plurality of guide rolls excluding the lead-forming part; and the step of moving at least one selected from the gravure roll and the guide rolls to make the electrode sheet away from the gravure roll in the lead-forming part.
    Type: Application
    Filed: August 11, 2009
    Publication date: June 24, 2010
    Applicant: Panasonic Corporation
    Inventors: Yusuke FUKUMOTO, Tsumoru OHATA, Tetsuya HAYASHI
  • Patent number: 7714352
    Abstract: A semiconductor device, includes: a first conductivity-semiconductor substrate; a hetero semiconductor region for forming a hetero junction with the first conductivity-semiconductor substrate; a gate electrode adjacent to a part of the hetero junction by way of a gate insulating film; a drain electrode connecting to the first conductivity-semiconductor substrate; a source electrode connecting to the hetero semiconductor region; and a second conductivity-semiconductor region formed on a part of a first face of the first conductivity-semiconductor substrate in such a configuration as to oppose the gate electrode via the gate insulating film, the gate insulating film, the hetero semiconductor region and the first conductivity-semiconductor substrate contacting each other to thereby form a triple contact point.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: May 11, 2010
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Yoshio Shimoida, Masakatsu Hoshi, Tetsuya Hayashi, Hideaki Tanaka, Shigeharu Yamagami
  • Publication number: 20100111486
    Abstract: The present invention relates to a dispersion compensating module having a configuration that can effectively suppress high-speed fluctuations in the polarization state of light even when being imparted with impact or vibration. In the dispersion compensating module, a dispersion compensating optical fiber is fixed while being wound around the barrel of a bobbin, and the bobbin is fixed in the inside of a housing via a buffer that absorbs impact or vibration. The bobbin corresponds to a holder holding the dispersion compensating optical fiber fixed in a state of coil. The housing corresponds to a struct fixing the holder. The buffer fills a space between the housing and the bobbin on which the dispersion compensating optical fiber is coiled.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 6, 2010
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Tetsuya HAYASHI, Eisuke SASAOKA, Kazuya KUWAHARA, Takashi SASAKI, Yasushi KOYANO, Fumiyoshi OHKUBO, Shinjiro HAGIHARA
  • Patent number: 7696839
    Abstract: A signal waveform equalizer circuit capable of equalizing the waveform of an input signal with a center voltage of 0 V and yet small in circuit scale. An input signal (in FIG. 1, positive-phase input signal) whose waveform is to be equalized is input to the source of an nMOS, and this enables the equalizer circuit to handle an input signal with the center voltage 0 V without the need to add an extra circuit. The waveform of the input signal is shaped by a delay circuit including a resistor and a capacitor, and an output signal (in FIG. 1, positive-phase output signal) is output from a node.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: April 13, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tetsuya Hayashi, Tomokazu Higuchi