Patents by Inventor Tetsuya Nitta
Tetsuya Nitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210288145Abstract: Provided is a semiconductor device having improved breakdown resistance during recovery operation. A semiconductor device according to the present application is a semiconductor device in which an insulated gate bipolar transistor region and a diode region are provided adjacent to each other. The insulated gate bipolar transistor region includes an emitter layer having a short-side direction in a first direction in a plan view. The diode region includes carrier injection suppression layer having a short-side direction in a second direction in a plan view. In a plan view, a width of the carrier injection suppression layer in the second direction is smaller than a width of the emitter layer in the first direction.Type: ApplicationFiled: November 23, 2020Publication date: September 16, 2021Applicant: Mitsubishi Electric CorporationInventors: Ryu KAMIBABA, Shinya SONEDA, Tetsuya NITTA
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Publication number: 20210156461Abstract: Provided is a rotation drive device, which has a driving-force transmission mechanism configured such that a drive transmission member provided on a driving shaft and a disk-shaped driven member attached to a main shaft are directly or indirectly engaged with each other and which is further configured such that an increase in diameter of the driven member due to thermal expansion can be suppressed as much as possible. The driven member includes an inner ring attached to the main shaft, and an outer ring attached to the inner ring by shrinkage fit and having an engaging groove formed to be opened on an outer circumferential surface thereof. The inner ring is formed by a low thermal expansion member, which is an alloy having a thermal expansion coefficient of 5×10?6/K or less. The outer ring is formed of a hardenable iron-based material.Type: ApplicationFiled: October 26, 2020Publication date: May 27, 2021Applicant: TSUDAKOMA KOGYO KABUSHIKI KAISHAInventors: Tetsuya NITTA, Junichiro ISHIZAKI
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Publication number: 20210091216Abstract: An object is to provide a technique capable of improving both recovery loss and recovery capability. The semiconductor device includes a base layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the IGBT region and an anode layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the diode region. The anode layer includes a first portion having a lower end located at a same position as a lower end of the base layer or having a lower end located above the lower end of the base layer and a second portion adjacent to the first portion in plan view, and whose lower end is located above the lower end of the first portion.Type: ApplicationFiled: July 14, 2020Publication date: March 25, 2021Applicant: Mitsubishi Electric CorporationInventors: Shinya SONEDA, Ryu KAMIBABA, Tetsuya NITTA
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Publication number: 20210057529Abstract: According to an aspect of the present disclosure, a semiconductor device includes a semiconductor substrate, a lower electrode provided on the semiconductor substrate, an insulating film that is provided on the semiconductor substrate and surrounds the lower electrode and a metal film that is provided on the lower electrode and includes a convex portion on an upper surface thereof, wherein the convex portion includes a first portion extending in a first direction parallel to an upper surface of the semiconductor substrate, and a second portion extending in a second direction that is parallel to the upper surface of the semiconductor substrate and intersects the first direction, and the metal film is thinner than the insulating film.Type: ApplicationFiled: February 5, 2020Publication date: February 25, 2021Applicant: Mitsubishi Electric CorporationInventors: Shinya SONEDA, Tetsuya NITTA, Kenji HARADA
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Patent number: 10249708Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.Type: GrantFiled: October 6, 2017Date of Patent: April 2, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kosuke Yoshida, Tetsuya Nitta, Atsushi Sakai
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Patent number: 10128359Abstract: A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.Type: GrantFiled: January 13, 2017Date of Patent: November 13, 2018Assignee: Renesas Electronics CorporationInventors: Mikio Tsujiuchi, Tetsuya Nitta
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Patent number: 9972679Abstract: To provide a semiconductor device having improved performances. A semiconductor substrate has, in the surface layer portion thereof, an n+ type semiconductor region for source and an n+ type semiconductor region for drain separated from each other. The semiconductor substrate has, on the main surface thereof between the n+ type semiconductor region for source and the n+ type semiconductor region for drain, a gate electrode via an insulating film as a gate insulating film. The semiconductor substrate has, in the main surface thereof between the channel formation region below the gate electrode and the n+ type semiconductor region for drain, a LOCOS oxide film and an STI insulating. Of the LOCOS oxide film and the STI insulating film, the LOCOS oxide film is located on the side of the channel formation region and the STI insulating film is on the side of the n+ type semiconductor region DR for drain.Type: GrantFiled: February 12, 2015Date of Patent: May 15, 2018Assignee: Renesas Electronics CorporationInventors: Hajime Kataoka, Tatsuya Shiromoto, Tetsuya Nitta
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Publication number: 20180033855Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.Type: ApplicationFiled: October 6, 2017Publication date: February 1, 2018Inventors: Kosuke Yoshida, Tetsuya Nitta, Atsushi Sakai
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Patent number: 9881868Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.Type: GrantFiled: October 17, 2014Date of Patent: January 30, 2018Assignee: Renesas Electronics CorporationInventors: Shigeo Tokumitsu, Takahiro Mori, Tetsuya Nitta
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Publication number: 20170365553Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.Type: ApplicationFiled: September 6, 2017Publication date: December 21, 2017Applicant: Renesas Electronics CorporationInventors: Shigeo TOKUMITSU, Takahiro MORI, Tetsuya NITTA
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Patent number: 9806147Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.Type: GrantFiled: January 27, 2014Date of Patent: October 31, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kosuke Yoshida, Tetsuya Nitta, Atsushi Sakai
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Patent number: 9786594Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.Type: GrantFiled: October 17, 2014Date of Patent: October 10, 2017Assignee: Renesas Electronics CorporationInventors: Shigeo Tokumitsu, Takahiro Mori, Tetsuya Nitta
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Publication number: 20170125558Abstract: A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.Type: ApplicationFiled: January 13, 2017Publication date: May 4, 2017Applicant: Renesas Electronics CorporationInventors: Mikio TSUJIUCHI, Tetsuya NITTA
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Patent number: 9583604Abstract: A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.Type: GrantFiled: September 29, 2014Date of Patent: February 28, 2017Assignee: Renesas Electronics CorporationInventors: Mikio Tsujiuchi, Tetsuya Nitta
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Publication number: 20160181357Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (Si) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.Type: ApplicationFiled: January 27, 2014Publication date: June 23, 2016Inventors: Kosuke Yoshida, Tetsuya Nitta, Atsushi Sakai
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Patent number: 9356135Abstract: To provide a semiconductor device capable of suppressing a reduction in breakdown voltage by suppressing a change in dimensions of a double RESURF structure, and a method of manufacturing the same. In the semiconductor device, an upper RESURF region is formed so as to contact with a first buried region on a side of the one main surface within a semiconductor substrate. The semiconductor substrate has a field oxide formed so as to reach the upper RESURF region on the one main surface. The semiconductor substrate includes a second conductivity type body region formed so as to contact with the upper RESURF region on a side of the one main surface and so as to neighbor the field oxide within the semiconductor substrate.Type: GrantFiled: January 26, 2015Date of Patent: May 31, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kosuke Yoshida, Tetsuya Nitta
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Publication number: 20150380532Abstract: In a current-prioritized IGBT, a collector conductive layer is connected to one collector active region included in a collector region by a plurality of contacts. The number of contacts through which the collector conductive layer is connected to the one collector active region is larger than the number of contacts through which the emitter conductive layer is connected to one base active region included in a base region.Type: ApplicationFiled: September 9, 2015Publication date: December 31, 2015Inventors: Mikio TSUJIUCHI, Tetsuya NITTA
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Patent number: 9153673Abstract: In a current-prioritized IGBT, a collector conductive layer is connected to one collector active region included in a collector region by a plurality of contacts. The number of contacts through which the collector conductive layer is connected to the one collector active region is larger than the number of contacts through which the emitter conductive layer is connected to one base active region included in a base region.Type: GrantFiled: February 16, 2012Date of Patent: October 6, 2015Assignee: Renesas Electronics CorporationInventors: Mikio Tsujiuchi, Tetsuya Nitta
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Patent number: RE46773Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.Type: GrantFiled: April 7, 2016Date of Patent: April 3, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii
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Patent number: RE48450Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.Type: GrantFiled: March 13, 2018Date of Patent: February 23, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii