Abstract: To provide a semiconductor device having improved performances. A semiconductor substrate has, in the surface layer portion thereof, an n+ type semiconductor region for source and an n+ type semiconductor region for drain separated from each other. The semiconductor substrate has, on the main surface thereof between the n+ type semiconductor region for source and the n+ type semiconductor region for drain, a gate electrode via an insulating film as a gate insulating film. The semiconductor substrate has, in the main surface thereof between the channel formation region below the gate electrode and the n+ type semiconductor region for drain, a LOCOS oxide film and an STI insulating. Of the LOCOS oxide film and the STI insulating film, the LOCOS oxide film is located on the side of the channel formation region and the STI insulating film is on the side of the n+ type semiconductor region DR for drain.

Abstract: To provide a semiconductor device capable of suppressing a reduction in breakdown voltage by suppressing a change in dimensions of a double RESURF structure, and a method of manufacturing the same. In the semiconductor device, an upper RESURF region is formed so as to contact with a first buried region on a side of the one main surface within a semiconductor substrate. The semiconductor substrate has a field oxide formed so as to reach the upper RESURF region on the one main surface. The semiconductor substrate includes a second conductivity type body region formed so as to contact with the upper RESURF region on a side of the one main surface and so as to neighbor the field oxide within the semiconductor substrate.

Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.

Abstract: A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.

Abstract: In a current-prioritized IGBT, a collector conductive layer is connected to one collector active region included in a collector region by a plurality of contacts. The number of contacts through which the collector conductive layer is connected to the one collector active region is larger than the number of contacts through which the emitter conductive layer is connected to one base active region included in a base region.

Abstract: To provide, in a semiconductor device formed on an SOI substrate and having a semiconductor layer of the SOI substrate surrounded, at the periphery of the element region thereof, with element isolation, a technology capable of preventing reliability deterioration attributed to the element isolation. Appearance of a hollow, which is formed upon filling of a deep trench with an insulating film, from the upper surface of the insulating film can be prevented by setting the trench width of the upper portion of the deep trench configuring trench isolation at less than 1.2 ?m. Reduction in the breakdown voltage between adjacent element regions which may presumably occur due to a decrease in the trench width of the upper portion of the deep trench can be prevented by forming, on the upper portion of the deep trench, an LOCOS insulating film coupled to the insulating film filled in the deep trench.

Abstract: The semiconductor device includes: a semiconductor substrate; a pair of injection elements; an active barrier structure; and a p-type ground region. The semiconductor substrate has a main surface and a p-type region formed therein. The active barrier structure is arranged in a region sandwiched between the pair of injection elements over the main surface. The p-type ground region is a ground potential-applicable region which is formed closer to an end side of the main surface than the pair of injection elements and the active barrier structure, bypassing a region sandwiched between the pair of injection elements over the main surface, and which is electrically coupled to the p-type region. The p-type ground region is divided by a region adjacent to the region sandwiched between the pair of injection elements.

Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

Abstract: In a semiconductor device, at least one of the ratio (collector contact area/collector active area) in the High Side IGBT and the ratio (contact area on p+ region/p+ region area) is higher than the ratio in the Low Side IGBT. Thus, it is possible to develop without substantial changes and reduce the development burden.

Abstract: To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.

Abstract: In a semiconductor device, at least one of the ratio (collector contact area/collector active area) in the High Side IGBT and the ratio (contact area on p+ region/p30 region area) is higher than the ratio in the Low Side IGBT. Thus, it is possible to develop without substantial changes and reduce the development burden.

Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

Abstract: There is provided a semiconductor device capable of suppressing malfunction of an element to be protected, caused by electrons from an output element into a semiconductor substrate. The semiconductor device is provided with the semiconductor substrate, the output element, the element to be protected, a tap part, and a first active-barrier structure. The first active-barrier structure is disposed between the element to be protected and the tap part. Further, the first active-barrier structure includes an n-type region joined with a p-type doped region, and a p-type region in ohmic coupling with the n-type region.

Abstract: The semiconductor device includes: a semiconductor substrate; a pair of injection elements; an active barrier structure; and a p-type ground region. The semiconductor substrate has a main surface and a p-type region formed therein. The active barrier structure is arranged in a region sandwiched between the pair of injection elements over the main surface. The p-type ground region is a ground potential-applicable region which is formed closer to an end side of the main surface than the pair of injection elements and the active barrier structure, bypassing a region sandwiched between the pair of injection elements over the main surface, and which is electrically coupled to the p-type region. The p-type ground region is divided by a region adjacent to the region sandwiched between the pair of injection elements.

Abstract: To provide, in a semiconductor device formed on an SOI substrate and having a semiconductor layer of the SOI substrate surrounded, at the periphery of the element region thereof, with element isolation, a technology capable of preventing reliability deterioration attributed to the element isolation. Appearance of a hollow, which is formed upon filling of a deep trench with an insulating film, from the upper surface of the insulating film can be prevented by setting the trench width of the upper portion of the deep trench configuring trench isolation at less than 1.2 ?m. Reduction in the breakdown voltage between adjacent element regions which may presumably occur due to a decrease in the trench width of the upper portion of the deep trench can be prevented by forming, on the upper portion of the deep trench, an LOCOS insulating film coupled to the insulating film filled in the deep trench.

Abstract: There is provided a semiconductor device capable of suppressing malfunction of an element to be protected, caused by electrons from an output element into a semiconductor substrate. The semiconductor device is provided with the semiconductor substrate, the output element, the element to be protected, a tap part, and a first active-barrier structure. The first active-barrier structure is disposed between the element to be protected and the tap part. Further, the first active-barrier structure includes an n-type region joined with a p-type doped region, and a p-type region in ohmic coupling with the n-type region.

Abstract: An N-layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N-layer, a trench isolation region is formed to surround the N-layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N-layer. Between trench isolation region and the N-layer, a P type diffusion region 10a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N-layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.

Abstract: An N? layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N? layer, a trench isolation region is formed to surround the N? layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N? layer. Between trench isolation region and the N? layer, a P type diffusion region 10a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N? layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.

Abstract: To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.

Abstract: An index table assembly includes a rotary table, a frame separated from the rotary table in the direction of a rotational axis of the rotary table, a clamping device for bringing the rotary table into contact with the frame by moving the rotary table along the rotational axis, a first bearing disposed between the rotary table and the frame, and an urging device disposed between the first bearing and one of the rotary table and the frame and pressing the first bearing against the other one of the rotary table and the frame at least when the rotary table rotates.