Patents by Inventor Tetsuya Nitta

Tetsuya Nitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040145027
    Abstract: An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.
    Type: Application
    Filed: July 24, 2003
    Publication date: July 29, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Tetsuya Nitta, Tomohide Terashima
  • Publication number: 20030132450
    Abstract: A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region (4) or n-type drift region (3) located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions (4) and n-type drift regions (3) forming the pn-repeating structure.
    Type: Application
    Filed: October 17, 2002
    Publication date: July 17, 2003
    Inventors: Tadaharu Minato, Tetsuya Nitta
  • Patent number: 6518144
    Abstract: The elements and the trenches are arranged alternately, in repetition, on the main surface of a semiconductor substrate, each of the plurality of elements arranged alternately, in repetition, with the trenches has a configuration (for example, STM) which operates in the same operational mode, and an insulating layer, which is filled into the trenches, and doesn't have a void at a position (the position shallower than the broken line L) shallower than the pn junction to which the largest electric field in the element is applied. Thereby, a semiconductor device and a process for the same, where voids inside of the trenches can be reduced and the film thickness of the insulating film, for filling in the trenches which remain on the surface of the semiconductor substrate, can be made thinner, can be gained through a simple method.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: February 11, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Nitta, Tadaharu Minato
  • Publication number: 20020040994
    Abstract: The elements and the trenches are arranged alternately, in repetition, on the main surface of a semiconductor substrate, each of the plurality of elements arranged alternately, in repetition, with the trenches has a configuration (for example, STAW which operates in the same operational mode, and an insulating layer, which is filled into the trenches, and doesn't have a void at a position (the position shallower than the broken line L) shallower than the pn junction to which the largest electric field in the element is applied. Thereby, a semiconductor device and a process for the same, where voids inside of the trenches can be reduced and the film thickness of the insulating film, for filng in the trenches which remain on the surface of the semiconductor substrate, can be made thinner, can be gained through a simple method.
    Type: Application
    Filed: March 22, 2001
    Publication date: April 11, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Nitta, Tadaharu Minato
  • Patent number: 6307246
    Abstract: A semiconductor substrate has a first main surface with a plurality of trenches 5a sandwiching a region in which p and n diffusions regions 2 and 3 are formed to provide a p-n junction along the depth of the trenches. P diffusion region 2 has a doping concentration profile provided by a p dopant diffused from a sidewall surface of one trench 5a, and n diffusion region 3 has a doping concentration profile provided by an n dopant diffused from a sidewall surface of the other trench 5a. A heavily doped n+ substrate region 1 is provided at a second main surface side of p and n diffusion regions 2 and 3. A depth Ld of trench 5a from the first main surface is greater than a depth Nd of p and n diffusion regions 2, 3 from the first main surface by at least a diffusion length L of the p dopant in p diffusion region 2 or the n dopant in n diffusion region 3 in manufacturing the semiconductor device. A high withstand voltage and low ON-resistance semiconductor device can thus be obtained.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: October 23, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Nitta, Tadaharu Minato, Akio Uenisi