Abstract: An energy storage system having a number of trays with each tray having a number of battery cells in which power is controllably stored and discharged. A first Battery Management System (BMS) is electrically coupled to a tray contained in a rack of trays. A second BMS is electrically coupled to and controls the first BMS. The first BMS includes a control unit electrically coupled to and controlling the battery cells. It further includes a switch unit electrically coupled to the control unit and selectively applying driving power according to a control signal from the second BMS.

Abstract: Provided is a semiconductor device having an anode of a Si-FRD and a cathode of a Si-SBD which are serially connected. The Si-SBD has a junction capacitance whose amount of accumulable charge is equal to or more than an amount of charge occurring at the time of reverse recovery of the Si-FRD, and has a lower breakdown voltage than the Si-FRD does.

Abstract: A battery system is disclosed. In one embodiment, the system includes i) a plurality of battery modules each of which is configured to store power, wherein each battery module is electrically connected to at least one other battery module and ii) a plurality of management units configured to monitor states of the battery modules. Each management unit is electrically connected to at least one other management unit and one or more of the battery modules. Each management unit may include: at least one measuring unit configured to perform the monitoring and a receiving unit configured to i) receive measurement data including the monitoring results from the measuring unit via a first communication protocol and ii) receive measurement data from another receiving unit included in another management unit via a second communication protocol different from the first communication protocol.

Abstract: An apparatus for detecting leakage current of a battery is disclosed. The apparatus includes a leakage current generating unit, a leakage current measuring unit, and a peak holding unit.

Abstract: A battery system having components with reduced maximum voltage tolerance requirements is disclosed. The battery system includes a battery pack with battery modules, and measuring units, which are connected to the battery modules. The measuring units have first analog front ends (AFEs) for monitoring the at least two battery modules. Each first AFE is configured to transmit information related to the monitored characteristic via an isolator to a processor configured to control the battery pack based on the transmitted information. The isolator receives the transmitted information from an AFE which is not connected to the battery module having the least electric potential or to the battery module having the greatest electric potential.

Abstract: In a pn junction diode having a conductivity modulating element provided on a first principal surface of a semiconductor substrate, when an impurity concentration of a p type impurity region is lowered to shorten a reverse recovery time, hole injection is suppressed, thereby causing a problem that a forward voltage value is increased at a certain current point. Moreover, introduction of a life time killer to shorten the reverse recovery time leads to a problem of increased leak current. On an n? type semiconductor layer that is a single crystal silicon layer, a p type polycrystalline silicon layer (p type polysilicon layer) is provided. Since the polysilicon layer has more grain boundaries than the single crystal silicon layer, an amount of holes injected into the n? type semiconductor layer from the p type polysilicon layer in forward voltage application can be suppressed.

Abstract: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.

Abstract: A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R1, R2, R3, . . . , Rx represent the area ratio R of each of the projecting patterns with respect to the corresponding substrates, and T1, T2, T3, . . .

Abstract: A battery multi-series system and a communication method thereof. The battery multi-series system includes a master battery management system managing a battery; and a block master battery management system connected to the master battery management system and receiving data from at least one slave battery management system and storing the received data, wherein the master battery management system receives data periodically from the block master battery management system.

Abstract: A battery pack is disclosed that includes a plurality of battery cells and a plurality of temperature sensors. Each of the temperature sensors is for sensing a temperature of a corresponding one or more of the battery cells to generate a temperature signal, and the temperature sensors are divided into groups of temperature sensors. A plurality of A/D converters is provided, and each of the A/D converters is coupled to a corresponding one of the groups of temperature sensors to convert the temperature signal into a digital signal. An identification signal module is coupled to the A/D converters for applying different identification signals to the plurality of A/D converters, respectively. A controller is coupled to the A/D converters for receiving the identification signals and the temperature signal, and for identifying a temperature of each of the battery cells through the identification signals.

Abstract: A battery pack having a function for preventing operation of the battery pack when an abnormal replacement of a battery cell is detected or preventing a use of the battery pack in which a cap has been removed. The battery pack generates an encryption code and writes the encryption code to data flash when a battery cell is normally discharged according to a first voltage, and if an abnormal power-on reset is detected on the battery cell, the battery pack may check the stored encryption code to a second encryption code generated upon power-on reset. If the codes do not match, firmware of the battery pack is deleted and/or a fuse is blown, making it is possible to prevent the battery pack from being re-used when the battery cell has been replaced or in which a cap has been removed.

Abstract: Provided is a semiconductor device in which an insulating region surrounding an element region is provided in an end portion of a semiconductor region with a super junction structure. Since a depletion layer in the element region ends in the insulating region, the end portion of the element region is not formed in a curved surface shape. In other words, the depletion layer has no curved surface in which internal electric fields are concentrated. For this reason, there is no need to take a measure to cause the depletion layer to spread in a horizontal direction by proving a terminal region. Since the terminal region is unnecessary, a chip size can be reduced. Alternatively, an area of the element region can be expanded.

Abstract: When a pause request occurs, an audio delay time constituted by a delay time of frames of audio data based on the video data frames is found. During the pause, a frame offset time constituted by the offset of the frame start time of the video data and the audio data is monitored. When a pause release request is issued, based on the audio delay time and the frame offset time, the audio correction time to be corrected in the pause request is calculated. Then, when it is judged that the audio data is advanced with respect to the video data based on the audio correction time cumulatively added for each pause request, the video data is delayed by one frame with respect to the audio data, while when it is judged that the audio data is delayed with respect to the video data, the audio data is delayed by one frame with respect to the video data.

Abstract: A packet processing apparatus includes a packet processing engine and a search engine connected through a bus having a bandwidth which is equal to or greater than a total transmission bandwidth of one or more receiving ports. The packet processing engine is configured to append a device internal header containing a search key to each of the packets, transfer the packets to the search engine through the bus, and receive the packets whose device internal headers are provided with search result information from the search engine through the bus. The search engine includes a packet buffer for temporarily storing the packets, a search processing part for performing search processing on the basis of the search key in the device internal header, and means for transferring the search result information from the search processing part and the packets stored in the packet buffer to the packet processing engine.

Abstract: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.

Abstract: In a pn junction diode having a conductivity modulating element provided on a first principal surface of a semiconductor substrate, when an impurity concentration of a p type impurity region is lowered to shorten a reverse recovery time, hole injection is suppressed, thereby causing a problem that a forward voltage value is increased at a certain current point. Moreover, introduction of a life time killer to shorten the reverse recovery time leads to a problem of increased leak current. On an n? type semiconductor layer that is a single crystal silicon layer, a p type polycrystalline silicon layer (p type polysilicon layer) is provided. Since the polysilicon layer has more grain boundaries than the single crystal silicon layer, an amount of holes injected into the n? type semiconductor layer from the p type polysilicon layer in forward voltage application can be suppressed.

Abstract: A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R1, R2, R3, . . . , Rx represent the area ratio R of each of the projecting patterns with respect to the corresponding substrates, and T1, T2, T3, . . .

Abstract: Provided is a semiconductor device in which an insulating region surrounding an element region is provided in an end portion of a semiconductor region with a super junction structure. Since a depletion layer in the element region ends in the insulating region, the end portion of the element region is not formed in a curved surface shape. In other words, the depletion layer has no curved surface in which internal electric fields are concentrated. For this reason, there is no need to take a measure to cause the depletion layer to spread in a horizontal direction by proving a terminal region. Since the terminal region is unnecessary, a chip size can be reduced. Alternatively, an area of the element region can be expanded.

Abstract: A smart battery pack and a method for recognizing the battery type using the same. The smart battery pack includes at least one battery cell coupled to an external set via positive and negative electrode terminals. A timer circuit is coupled to the external set via a data terminal and is adapted to apply a predetermined timer circuit signal for a period of time when a predetermined signal is applied from the external set. A first switch is controlled by the timer circuit and applies electric power from the battery cell, and a register outputs a predetermined register signal causing a smart battery controller to output battery type information to the external set. The smart battery pack has only one data line between the smart battery pack and the external set (and one data terminal on each) facilitating communication between the devices while maintaining a reduced manufacturing cost.

Abstract: A second electrode is selectively brought into contact with a semiconductor substrate. Specifically, an insulating film having opening portions is provided on the second principal surface of the semiconductor substrate, and the second electrode is provided on the insulating film. The second electrode comes into contact with the second principal surface of the semiconductor substrate through the opening portions. The total area of the opening portions is approximately the half of the total area of the second principal surface of the semiconductor substrate. Consequently, minority carriers (holes) are prevented by the insulating film from being drawn out, and thus, the loss of the minority carriers around the second electrode is decreased. Accordingly, the conductivity modulation effect is improved. Therefore, the forward voltage can be decreased even with a structure in which the impurity concentration of a p type impurity region is decreased in order to shorten a reverse recover time.