Patents by Inventor Tetsuya Okada

Tetsuya Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7417295
    Abstract: Two metal electrode layers are provided. A first electrode layer is patterned with a minute separation distance according to an element region as in the case of the conventional case. Meanwhile, it suffices that a second electrode layer be in contact with the first electrode layer. Thus, no problems arise even if the separation distance is elongated. Specifically, the second electrode layer can be set to have a desired thickness. Moreover, by disposing a nitride film on the first electrode layer below a wire bonding region, even when volume expansion is caused by an Au/Al eutectic layer, transmission of stress to the element region can be prevented.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: August 26, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kazunari Kushiyama, Tetsuya Okada, Makoto Oikawa
  • Patent number: 7399999
    Abstract: In a conventional semiconductor device, there was a problem that, in a guard ring region, a shape of a depletion layer is distorted and stable withstand voltage characteristics cannot be obtained. In a semiconductor device of the present invention, a thermal oxide film in an actual operation region and a thermal oxide film in a guard ring region are formed in the same process. Thereafter, the thermal oxide film is once removed and is formed again. Thus, a film thickness of the thermal oxide film on the upper surface of the guard ring region is set to, for example, about 8000 to 10000 ?. Accordingly, a CVD oxide film including moving ions is formed in a position distant from a surface of an epitaxial layer. Consequently, distortion of a depletion layer, which is influenced by the moving ions, is suppressed and desired withstand voltage characteristics can be maintained.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: July 15, 2008
    Assignees: Sanyo Electric Co., Ltd., Gifu Sanyo Electronics Co., Ltd.
    Inventors: Tetsuya Yoshida, Tetsuya Okada, Hiroaki Saito, Shigeyuki Murai, Kikuo Okada
  • Publication number: 20080038880
    Abstract: There is the need to grind a semiconductor substrate from its back surface in order to thin a drift region for forming the NPT type IGBT. A collector region is then formed on the back surface of the semiconductor substrate by performing ion-implantation, a heat treatment and the like to the back surface of the semiconductor substrate of which the strength is weakened. This causes problems of warping the semiconductor substrate and the like. In a method of manufacturing a semiconductor device of the invention, the thickness of a drift region is previously adjusted by the thickness of an epitaxial layer. A collector region is then formed only by grinding a semiconductor substrate. In particular, using a semiconductor substrate containing a low concentration of impurity provides preferable characteristics for a high-speed switching element with a short turn-off time even when the collector region is thick.
    Type: Application
    Filed: August 6, 2007
    Publication date: February 14, 2008
    Inventors: Kikuo Okada, Tetsuya Okada
  • Publication number: 20070160052
    Abstract: A packet processing apparatus includes a packet processing engine and a search engine connected through a bus having a bandwidth which is equal to or greater than a total transmission bandwidth of one or more receiving ports. The packet processing engine is configured to append a device internal header containing a search key to each of the packets, transfer the packets to the search engine through the bus, and receive the packets whose device internal headers are provided with search result information from the search engine through the bus. The search engine includes a packet buffer for temporarily storing the packets, a search processing part for performing search processing on the basis of the search key in the device internal header, and means for transferring the search result information from the search processing part and the packets stored in the packet buffer to the packet processing engine.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 12, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Tetsuya Okada
  • Publication number: 20070072352
    Abstract: A separation hole is provided in the center of the gate electrode. Accordingly, it is possible to suppress a drastic increase in feedback capacitance Crss in the case where drain-source voltage VDS is decreased and the width of the depletion layer is narrowed. Thus, high-frequency switching characteristics are improved. Moreover, n type impurities are implanted from the separation hole to form an n type impurity region between channel regions. Since a resistance in a portion below the gate electrode can be reduced, an on-resistance can be reduced. The n type impurity region can be formed in a self-aligning manner.
    Type: Application
    Filed: September 12, 2006
    Publication date: March 29, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Kazunari Kushiyama, Tetsuya Okada, Makoto Oikawa, Hiroyasu Ishida, Yasuyuki Sayama
  • Publication number: 20070034943
    Abstract: Two metal electrode layers are provided. A first electrode layer is patterned with a minute separation distance according to an element region as in the case of the conventional case. Meanwhile, it suffices that a second electrode layer be in contact with the first electrode layer. Thus, no problems arise even if the separation distance is elongated. Specifically, the second electrode layer can be set to have a desired thickness. Moreover, by disposing a nitride film on the first electrode layer below a wire bonding region, even when volume expansion is caused by an Au/Al eutectic layer, transmission of stress to the element region can be prevented.
    Type: Application
    Filed: August 1, 2006
    Publication date: February 15, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Kazunari Kushiyama, Tetsuya Okada, Makoto Oikawa
  • Publication number: 20060220122
    Abstract: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.
    Type: Application
    Filed: March 13, 2006
    Publication date: October 5, 2006
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Yasuyuki Sayama, Tetsuya Okada, Makoto Oikawa, Hiroyasu Ishida, Kazunari Kushiyama
  • Patent number: 7114151
    Abstract: Interlocked floating-point instructions are detected, and a register address referring to and assigning an operand in the interlocked instructions is changed to an odd-number address not assigned as any operation at the time of compiling. Next, an instruction not in any register-dependency relation with the interlocked instructions is detected, and the detected instruction is inserted between instructions interlocked with each other. Thus a program can be executed with an improved efficiency.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: September 26, 2006
    Assignee: Sony Corporation
    Inventor: Tetsuya Okada
  • Publication number: 20060140280
    Abstract: When a pause request occurs, an audio delay time constituted by a delay time of frames of audio data based on the video data frames is found. During the pause, a frame offset time constituted by the offset of the frame start time of the video data and the audio data is monitored. When a pause release request is issued, based on the audio delay time and the frame offset time, the audio correction time to be corrected in the pause request is calculated. Then, when it is judged that the audio data is advanced with respect to the video data based on the audio correction time cumulatively added for each pause request, the video data is delayed by one frame with respect to the audio data, while when it is judged that the audio data is delayed with respect to the video data, the audio data is delayed by one frame with respect to the video data.
    Type: Application
    Filed: June 3, 2004
    Publication date: June 29, 2006
    Applicant: Sony Corporation
    Inventors: Tetsuya Okada, Daisuke Hiranaka
  • Patent number: 7034376
    Abstract: A Schottky barrier diode in which a p+-type semiconductor layer is provided in an n?-type epitaxial layer can realize lowering the forward voltage VF without considering leak current IR. However, when compared with a normal Schottky barrier diode, the forward voltage VF is generally high. When a Schottky metal layer is suitably selected, although the forward voltage VF can be reduced, there is a limit in further reduction. On the other hand, when the resistivity of the n?-type semiconductor layer is reduced, although the forward voltage VF can be realized, there is a problem that breakdown voltage is deteriorated. In a semiconductor device of the invention, a second n?-type semiconductor layer having a low resistivity is laminated on a first n?-type semiconductor layer capable of securing a specified breakdown voltage. P+-type semiconductor regions are made to have depths equal to or slightly deeper than the second n?-type semiconductor layer.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: April 25, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuya Okada, Hiroaki Saito
  • Publication number: 20060076924
    Abstract: A smart battery pack and a method for recognizing the battery type using the same. The smart battery pack includes at least one battery cell coupled to an external set via positive and negative electrode terminals. A timer circuit is coupled to the external set via a data terminal and is adapted to apply a predetermined timer circuit signal for a period of time when a predetermined signal is applied from the external set. A first switch is controlled by the timer circuit and applies electric power from the battery cell, and a register outputs a predetermined register signal causing a smart battery controller to output battery type information to the external set. The smart battery pack has only one data line between the smart battery pack and the external set (and one data terminal on each) facilitating communication between the devices while maintaining a reduced manufacturing cost.
    Type: Application
    Filed: August 30, 2005
    Publication date: April 13, 2006
    Inventors: Jong Kim, Tetsuya Okada
  • Publication number: 20050218472
    Abstract: A trench is provided, which penetrates a channel layer between adjacent gate electrodes in a MOSFET, and a Schottky metal layer is provided in the trench. Accordingly, a bottom of the trench becomes a Schottky barrier diode. Thus, the Schottky barrier diode can be included in a diffusion region of the MOSFET. Consequently, miniaturization of the device and reduction in the number of components can be realized.
    Type: Application
    Filed: March 28, 2005
    Publication date: October 6, 2005
    Applicant: Sanyo Electric Co., Ltd
    Inventors: Tetsuya Okada, Akihiko Funakoshi
  • Publication number: 20050184355
    Abstract: Conventionally, a guard ring for securing a breakdown voltage is provided around a Schottky barrier diode. Since the guard ring is a p+ type region, a depletion layer expands around the guard ring when a reverse voltage is applied to prevent a reduction in capacitance. In addition, there is a problem in that, when a forward voltage is applied, holes are injected from the guard ring if the applied voltage exceeds a predetermined voltage and high-speed operation cannot be realized. To solve the problems, a trench is provided in a guard ring region of the conventional technique and an insulating film is provided inside the trench. The trench is provided to reach an n+ type semiconductor substrate. Consequently, since the depletion layer expands only in a depth direction until the depletion layer reaches the n+ type semiconductor substrate, it is possible to realize a reduction in capacitance. In addition, since the p+ type region is made unnecessary, a reverse recovery time (Trr) does not occur.
    Type: Application
    Filed: February 24, 2005
    Publication date: August 25, 2005
    Applicant: Sanyo Electric Co., Ltd.
    Inventor: Tetsuya Okada
  • Publication number: 20050184406
    Abstract: Conventionally, VF and IR characteristics of a Schottky barrier diode are in a tradeoff relation and there is a problem in that an increase in a leak current is unavoidable in order to realize a reduction in VF. To solve the problem, p type semiconductor regions of a pillar shape reaching an n+ type semiconductor substrate are provided in an n? type semiconductor layer. When a reverse voltage is applied, a depletion layer expanding in a substrate horizontal direction from the p type semiconductor regions fills the n? type semiconductor layer. Thus, it is possible to prevent the leak current generated on a Schottky junction interface from leaking to a cathode side.
    Type: Application
    Filed: February 22, 2005
    Publication date: August 25, 2005
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Tetsuya Okada, Hiroaki Saito
  • Publication number: 20050180643
    Abstract: When encoding and decoding are concurrently executed by sharing one image memory, the present invention is able to flexibly cope with a situation in which a change occurs in the image size subject to processing. A memory allocation processing block receives information about the image size and the number of images that are specified for each of encoding and decoding, individually allocates the memory areas corresponding to the specified image size by allocating these memory areas to the free area in the image memory in the number equivalent to the number of images, and outputs the addresses of the allocated memory areas.
    Type: Application
    Filed: February 3, 2005
    Publication date: August 18, 2005
    Inventor: Tetsuya Okada
  • Publication number: 20050139947
    Abstract: A Schottky barrier diode in which a p+-type semiconductor layer is provided in an n?-type epitaxial layer can realize lowering the forward voltage VF without considering leak current IR. However, when compared with a normal Schottky barrier diode, the forward voltage VF is generally high. When a Schottky metal layer is suitably selected, although the forward voltage VF can be reduced, there is a limit in further reduction. On the other hand, when the resistivity of the n?-type semiconductor layer is reduced, although the forward voltage VF can be realized, there is a problem that breakdown voltage is deteriorated. In a semiconductor device of the invention, a second n?-type semiconductor layer having a low resistivity is laminated on a first n?-type semiconductor layer capable of securing a specified breakdown voltage. P+-type semiconductor regions are made to have depths equal to or slightly deeper than the second n?-type semiconductor layer.
    Type: Application
    Filed: September 30, 2004
    Publication date: June 30, 2005
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Tetsuya Okada, Hiroaki Saito
  • Publication number: 20050133814
    Abstract: In a conventional semiconductor device, there was a problem that, in a guard ring region, a shape of a depletion layer is distorted and stable withstand voltage characteristics cannot be obtained. In a semiconductor device of the present invention, a thermal oxide film in an actual operation region and a thermal oxide film in a guard ring region are formed in the same process. Thereafter, the thermal oxide film is once removed and is formed again. Thus, a film thickness of the thermal oxide film on the upper surface of the guard ring region is set to, for example, about 8000 to 10000 ?. Accordingly, a CVD oxide film including moving ions is formed in a position distant from a surface of an epitaxial layer. Consequently, distortion of a depletion layer, which is influenced by the moving ions, is suppressed and desired withstand voltage characteristics can be maintained.
    Type: Application
    Filed: October 6, 2004
    Publication date: June 23, 2005
    Applicants: Sanyo Electric Co., Ltd., Gifu SANYO Electronics Co., Ltd.
    Inventors: Tetsuya Yoshida, Tetsuya Okada, Hiroaki Saito, Shigeyuki Murai, Kikuo Okada
  • Publication number: 20050116283
    Abstract: In conventional semiconductor devices, there observed a problem that cells on the devices may not function uniformly because of voltage drop in a main wiring layer due to a uniform and narrow width of the main wiring layer through which a main current flows. In a semiconductor device of the present invention, a width of one end of a main wire for carrying the main current is formed wider than a width of another end of the main wire. An overall width of the main wire is formed so as to be gradually narrowed from the one end to the another end. In this way, it is possible to reduce a difference in drive voltages between a cell located in the vicinity of an electrode pad for carrying the main current and a cell located in a remote position. Resultantly, it is possible to suppress a voltage drop in the main wire and to achieve uniform operations of cells in an element.
    Type: Application
    Filed: October 20, 2004
    Publication date: June 2, 2005
    Applicants: Sanyo Electric Co., Ltd., Gifu SANYO Electronics Co., Ltd.
    Inventors: Tetsuya Yoshida, Tetsuya Okada, Hiroaki Saito, Shigeyuki Murai, Kikuo Okada
  • Patent number: 6809354
    Abstract: In a semiconductor device, a variable-potential insulated electrode and a gate region are kept at the same potential through an aluminum layer. This device is mainly used as a voltage-driving type semiconductor device. By varying the voltage applied to the variable-potential insulated electrode through a gate electrode, a conductive path is formed in a channel region to switch on the device. The channel region turns into an N-type region when a positive potential is applied to the gate electrode, and turns into a pseudo P-type region when a ground potential or negative potential is applied to the gate electrode.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: October 26, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuya Okada, Mitsuhiro Yoshimura, Tetsuya Yoshida
  • Patent number: 6756768
    Abstract: Remaining battery capacity is computed by computing battery discharge capacity from an integrated value of a product of discharge current and voltage to find remaining battery capacity via energy (integrated power). Battery discharge capacity is computed by adding the integrated value of power consumed by internal resistance to a discharge capacity value calculated from the integrated product of discharge current and voltage, and the remaining battery capacity is computed from this battery discharge capacity.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: June 29, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Tetsuya Okada