Abstract: A fuel cell power generation system has

Abstract: A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrat

Abstract: A fuel cell electric power generating system is provided which does not occupy a large space, which requires a lower initial cost for equipment than the prior art, and of which the running cost is low. The system includes a reformer 1 producing hydrogen-rich gas by utilizing a source gas, source gas supplying means 3a of supplying the source gas to the reformer 1, air supplying means 5 of supplying purging air to the reformer, and a fuel cell 9 generating electric power by utilizing the hydrogen-rich gas produced at the reformer 1 and air for electric power generation supplied from outside, wherein in stopping the operation of the fuel cell 9, the supply of the source gas to the reformer 1 is stopped and the hydrogen-rich gas remaining within the fuel cell electric power generating system, steam and the purging air are passed in this order.

Abstract: A hydrogen producing apparatus comprising: a reforming section having a reforming catalyst which causes a reaction between a carbon-containing organic compound as a feedstock and water; a feedstock supply section for supplying the feedstock to the reforming section; a water supply section for supplying water to the reforming section; a heating section for heating the reforming catalyst; a shifting section having a shift catalyst which causes a shift reaction between carbon monoxide and water contained in a reformed gas supplied from the reforming section; and a purifying section having a purifying catalyst which causes oxidation or methanation of carbon monoxide contained in a gas supplied from the shifting section, wherein the shift catalyst comprises a platinum group metal and a metal oxide.

Abstract: After successively depositing a first metal film and a first silicon oxide film on an insulating film formed on a semiconductor substrate, etching is carried out by using a first resist pattern as a mask, so as to form a first interlayer insulating film having openings from the first silicon oxide film and first metal interconnects from the first metal film. A third interlayer insulating film of an organic film is filled in the openings of the first interlayer insulating film, and the first interlayer insulating film is etched by using a hard mask. A second metal film is then filled in a space in the second interlayer insulating film, so as to form second metal interconnects.

Abstract: An interconnect forming method includes the steps of: a) forming a through hole in an insulating film over a substrate; b) depositing a photosensitive masking material over the insulating film as well as inside the hole; c) patterning the material, thereby forming a mask pattern, which has an opening located over the hole and is used to define a trench; d) etching the insulating film to a predetermined depth using the mask pattern, thereby defining a trench pattern, linked to the hole, in an upper part of the insulating film; e) filling in the hole and the trench pattern with a conductive material; and f) before the trench pattern is defined, defining the mask pattern so that no remaining part of the material, which has been filled in the hole, will reach a level higher than the bottom of the trench pattern.

Abstract: After successively depositing a first metal film and a first silicon oxide film on an insulating film formed on a semiconductor substrate, etching is carried out by using a first resist pattern as a mask, so as to form a first interlayer insulating film having openings from the first silicon oxide film and first metal interconnects from the first metal film. A third interlayer insulating film of an organic film is filled in the openings of the first interlayer insulating film, and the first interlayer insulating film is etched by using a hard mask. A second metal film is then filled in a space in the second interlayer insulating film, so as to form second metal interconnects.

Abstract: In accordance with a fuel cell generation system of the present invention, an interior of a package 2 is partitioned into a gas path compartment 3 and a non gas compartment 4 with a partition wall 1, a component through which flammable gas flows is placed within the gas path compartment 3, a part of the frame member of the package 2 constituting the gas path compartment 3 is provided with gas path compartment inlets 12a and 12b, a gas path compartment outlet 13 and a ventilation fan 14, a component through which the flammable gas does not flows is placed within the non gas compartment 4, and a part of the frame member of the package 2 of the non gas compartment 4 is provided with a non gas compartment inlet 20, allowing a blower inlet 21 to open into an interior of the non gas compartment 4 and allowing an air outlet 22 to open into an exterior of the package 2.

Abstract: A semiconductor device includes metal interconnects made from a multi-layer film composed of a first metal film formed on a semiconductor substrate with an insulating film sandwiched therebetween and a second metal film deposited on the first metal film. An interlayer insulating film having a via hole is formed on the metal interconnects. A third metal film is selectively grown on the second metal film within the via hole, so that a plug can be formed from the third metal film.

Abstract: After a first metal film and a first interlayer insulating film are deposited successively on an insulating film on a semiconductor substrate, a via hole is formed in the first interlayer insulating film. A second metal film is grown in the via hole to form a via contact composed of the second metal film, while a recessed portion is formed over the via contact in the via hole. A cap layer composed of a material different from the material of the first metal film is formed in the recessed portion. Then, the first metal film is patterned by using a mask pattern for forming a lower interconnect and a cap layer as a mask, whereby a lower interconnect is formed.

Abstract: After a first metal film and a first interlayer insulating film are deposited successively on an insulating film on a semiconductor substrate, a via hole is formed in the first interlayer insulating film. A second metal film is grown in the via hole to form a via contact composed of the second metal film, while a recessed portion is formed over the via contact in the via hole. A cap layer composed of a material different from the material of the first metal film is formed in the recessed portion. Then, the first metal film is patterned by using a mask pattern for forming a lower interconnect and a cap layer as a mask, whereby a lower interconnect is formed.

Abstract: A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrat

Abstract: An interconnect forming method includes the steps of: a) forming a through hole in an insulating film over a substrate; b) depositing a photosensitive masking material over the insulating film as well as inside the hole; c) patterning the material, thereby forming a mask pattern, which has an opening located over the hole and is used to define a trench; d) etching the insulating film to a predetermined depth using the mask pattern, thereby defining a trench pattern, linked to the hole, in an upper part of the insulating film; e) filling in the hole and the trench pattern with a conductive material; and f) before the trench pattern is defined, defining the mask pattern so that no remaining part of the material, which has been filled in the hole, will reach a level higher than the bottom of the trench pattern.

Abstract: To prevent a void from being formed in a CMOS inverter due to electromigration. A power line 11 is connected to the source of a p-channel MOS transistor Tr1 via a first contact 12. A ground line 13 is connected to the source of an n-channel MOS transistor Tr2 via a second contact 14. One terminal of a first output signal line 15 is connected to the drain of the p-channel MOS transistor Tr1 via a third contact 16, while the other terminal thereof is connected to the drain of the n-channel MOS transistor Tr2 via a fourth contact 17. one terminal of a second output signal line 18 is connected to the fourth contact 17, while the other terminal thereof extends toward the output terminal of the inverter. A first path of an input signal line 19 is connected to the gate electrode 20 of the p-channel MOS transistor Tr1 via a fifth contact 21, while a second path thereof is connected to the gate electrode 20 of the n-channel MOS transistor Tr2 via a sixth contact 22.

Abstract: A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrat

Abstract: A method for fabricating a semiconductor device according to the present invention includes the steps of: a) forming an insulator film having Si—H bonds; b) forming a resist mask over a selected region of the insulator film; c) etching part of the insulator film that is not covered with the resist mask, thereby forming a recess in the insulator film; and d) removing the resist mask. The step d) includes the step of e) ashing the resist mask by using plasma produced from a gas comprising water vapor as a main component.

Abstract: A semiconductor device includes an encapsulating resin encapsulating a semiconductor substrate, a lead pattern or a laminated wiring layers transferred or secured on the lower surface of the encapsulating resin and a plurality of external electrode disposed on the lower surface of the lead pattern. The device may be manufactured by bonding a semiconductor substrate to a transferring substrate on which a lead pattern is formed, resin encapsulating an upper portion of the transferring substrate to cover the semiconductor substrate, and removing only the transferring substrate with the lead pattern left bonded to the encapsulating resin and the semiconductor substrate.

Abstract: There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate interconnections on both sides thereof. Between the gate electrode and the gate interconnections are located two first interspaces each of which is smaller in width than a specified value and a second interspace which is larger in width than the specified value and interposed between the two first interspaces. In forming side walls on both side faces of the gate electrode and gate interconnections by depositing an insulating film on the substrate, the first interspaces are buried with the insulating film. Thereafter, a metal film is deposited on the substrate, followed by chemical mechanical polishing till the gate electrode, gate interconnections, and side walls become exposed.

Abstract: A semiconductor device includes an encapsulating resin encapsulating a semiconductor substrate, a lead pattern or a laminated wiring layers transferred or secured on the lower surface of the encapsulating resin and a plurality of external electrode disposed on the lower surface of the lead pattern. The device may be manufactured by bonding a semiconductor substrate on a transferring substrate to which a lead pattern is formed, resin encapsulating an upper portion of the transferring substrate to cover the semiconductor substrate, and removing only the transferring substrate with the lead pattern left bonded to the encapsulating resin and the semiconductor substrate.

Abstract: A metal wire and a metal electrode which are composed of an aluminum alloy are formed on an interlayer insulating film composed of a silicon oxide film which is formed on the semiconductor substrate. On the entire surface of the metal wire and the metal electrode, a silicon oxide film and a silicon nitride film are formed serially, so as to compose a passivation film. A silicon nitrided-oxide layer is formed by nitriding a silicon oxide film in an area of the silicon oxide film which is the vicinity of the junction of either the metal wire or the metal electrode and the interlayer insulating film.